video

• https://www.youtube.com/watch?v=_1yrxrl61o4
• https://www.youtube.com/watch?v=kRTs6B-kEOE

git

dpavlin@klin:/klin/FPGA/CFU-Playground$ git remote -v
origin  https://github.com/google/CFU-Playground.git (fetch)
origin  https://github.com/google/CFU-Playground.git (push)
dpavlin@klin:/klin/FPGA/CFU-Playground$ git submodule init
dpavlin@klin:/klin/FPGA/CFU-Playground$ git submodule update

ulx3s board

https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/radiona_ulx3s.py

dpavlin@klin:/klin/FPGA/CFU-Playground$ find . -name radiona_ulx3s.py
./third_party/python/litex_boards/litex_boards/targets/radiona_ulx3s.py
./third_party/python/litex_boards/litex_boards/platforms/radiona_ulx3s.py
# edit fpga settings here
dpavlin@klin:/klin/FPGA/CFU-Playground$ vi ./third_party/python/litex_boards/litex_boards/targets/radiona_ulx3s.py

modifications for 85F litex-85f.diff

build

you really need riscv64 toolchain from https://github.com/sifive/freedom-tools/releases/tag/v2020.04.0-Toolchain.Only

dpavlin@klin:/klin/FPGA/CFU-Playground/proj$ cat build.sh
#!/bin/sh -xe

echo https://github.com/google/CFU-Playground

export PATH=/opt/riscv64-unknown-elf-gcc-8.3.0-2020.04.1-x86_64-linux-ubuntu14/bin/:$PATH
export TARGET=radiona_ulx3s
export UART_SPEED=115200
time make prog load

sumulation

dpavlin@klin:/klin/FPGA/CFU-Playground/proj/avg_pdti8$ time make PLATFORM=sim load -j 4

boot over serial using network

host with ulx3s connected

root@pihdmi:/home/pi# socat /dev/ttyUSB0,b115200,raw,echo=0 TCP:10.60.0.92:2003

machine running litex

dpavlin@klin:/klin/FPGA/CFU-Playground/proj/hps_accel$ socat TCP-LISTEN:2003 PTY,link=ttyV2,raw

1. re-run terminal with new virtal ttyV2

dpavlin@klin:/klin/FPGA/CFU-Playground/proj/hps_accel$ /klin/FPGA/CFU-Playground/soc/bin/litex_term --speed 115200  --serial-boot --kernel /klin/FPGA/CFU-Playground/proj/hps_accel/build/software.bin ttyV2

litex> serialboot
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
[LXTERM] Received firmware download request from the device.
[LXTERM] Uploading /klin/FPGA/CFU-Playground/proj/hps_accel/build/software.bin to 0x40000000 (1313688 bytes)...
[LXTERM] Upload complete (9.9KB/s).
[LXTERM] Booting the device.
[LXTERM] Done.
Executing booted program at 0x40000000

--============= Liftoff! ===============--
Hello, World!

Board version: v7.0

• Lattice ECP5 LFE5U-25F-6BG256C (product page)
• Winbond 25Q32JVSIQ, 32 Mbits SPI flash (datasheet)
• 2x Broadcom B50612D Gigabit Ethernet PHYs (datasheet)
• 2x ESMT M12L16161A-5T 1M x 16bit 200MHz SDRAMs (organized as 1M x 32bit) (datasheet)
• 12x 74HC245T Octal Bidirectional Transceiver (used for level translation to 5V)

links

• https://hackaday.com/2020/01/24/new-part-day-led-driver-is-fpga-dev-board-in-disguise/

chubby75

• https://github.com/q3k/chubby75/tree/master/5a-75b
• upstream: https://github.com/tomverbeure/chubby75/tree/5a-75b/5a-75b
• upstream for v7 board: https://github.com/miek/chubby75/blob/5a-75b-v7_pinout/5a-75b/hardware_V7.0.md

original protocol

• send data to original fpga image: https://github.com/FalconChristmas/fpp/blob/master/src/channeloutput/ColorLight-5a-75.cpp

replace level shifters to get input

• https://twitter.com/edu_arana/status/1231466891354525698

https://twitter.com/Claude1079/status/1231194849350647808

 SN74CBT3245APW 8bit bidirectional FET switches
QS3245QG

chiselwatt

https://github.com/antonblanchard/chiselwatt/commit/5a7fcbc8142ed2b390e1f8bfaaa801fe09a60351

UART RX is on J19, labelled key+ on the silk screen on the back
UART TX is on J1, pin 1.

LOCATE COMP "clock" SITE "P6";

LOCATE COMP "io_tx" SITE "F3";
LOCATE COMP "io_rx" SITE "M13";

litex

basic example of litex on colorLight 5A-75B based on fpga_101/lab004

• https://github.com/trabucayre/litexOnColorlightLab004/
• https://github.com/NiklasFauth/colorlight-led-cube
• https://github.com/ghent360/riscvOnColorlight-5A-75B

fpga pin mapping

https://twitter.com/adamgreig/status/1297255957320421383

I don't want to load a new image onto this totally blind, so I used the prjtrellis tools (https://github.com/YosysHQ/prjtrellis/) to write a script (https://github.com/adamgreig/cl/blob/master/pins.py) which works out input/output/bidi for all pins used in any ECP5 bitstream. It found only one unused pin...

https://github.com/adamgreig/cl/blob/master/pins.py

fpga images

• https://github.com/suglover/5a-75x-images
• ecpprog (FTDI jtag probe): https://github.com/gregdavill/ecpprog

List of useful (to me) FPGA resources:

Books

• http://www.freerangefactory.org/site/pmwiki.php/Main/Books (read all three of them, first two are VHDL)

Tools

• The ideal software tool to write, simulate and synthesize your VHDL code. https://code.google.com/p/boot-vhdl/

Projects

• http://hamsterworks.co.nz/mediawiki/index.php/Main_Page (great projects)
• FPGA-BASED USB INTERFACE http://www.xess.com/projects/FPGA-USB-V2/readmeusb-v2.php
• How-to debug internal FPGA Logic with the $50 Openbench Logic Sniffer. http://logicsniffer.gadgetfactory.net/index.php?n=LogicSniffer.DebugAnFPGA
• http://www.kickstarter.com/projects/1575992013/logi-fpga-development-board-for-raspberry-pi-beagl
• https://github.com/fpga-logi
• FPGA Arithmetic the way it should be http://flopoco.gforge.inria.fr/
• http://www.asics.ws/
• RGB video input for Altera DE1 board + PAL Modulator https://github.com/svofski/videoconditioner

• https://blackmesalabs.wordpress.com/2016/12/22/sump2-100-msps-32bit-logic-analyzer-for-icoboardraspberrypi/
• https://github.com/fpga-logi

X300 dongle

• Altera EPM3064A TC44-10N ftp://ftp.altera.com/outgoing/download/bsdl/3064at44.bsd
• LD1117A L33AUD

JTAG

I took picture of both sides of board, corrected it using perspective tool in gimp and added layers with VCC (5V and 3.3V) and GND (checked with unimer continuity test).

JTAG pinout doesn't match silkscreen designation of pin 1 (it's rotated). It also doesn't have VCC pin connected, so you need to supply 5V power via other means (I used PS/2 connector).

Bus Blaster jtag try:

jtag> cable jtagkey vid=0x0403 pid=0x6010 interface=0
Connected to libftd2xx driver.
jtag> detect
IR length: 10
Chain length: 1
Device Id: 00010111000001100100000011011101 (0x170640DD)
  Manufacturer: Altera (0x0DD)
  Part(0):      EPM3064A (0x7064)
  Stepping:     1
  Filename:     /usr/local/share/urjtag/altera/epm3064a/epm3064a

jtag> print chain
 No. Manufacturer              Part                 Stepping Instruction          Register
-------------------------------------------------------------------------------------------------------------------
*  0 Altera                    EPM3064A             1        BYPASS               BYPASS

# IMPORTANT: load signal aliases for this package
jtag> include /usr/local/share/urjtag/altera/epm3064a/t44

# get values of all pins

jtag> instruction SAMPLE/PRELOAD
jtag> shift ir
jtag> shift dr
jtag> dr
010010111010111010010111010010010010111111111010111010
111010010010010111010010010010010010010010010010010010
010010010010010010010010010010010010010010010010010010
010010010010010111010111010010
 (0x0000000000000000000000000000000024924924924975D2)

jtag> print chain
 No. Manufacturer              Part                 Stepping Instruction          Register
-------------------------------------------------------------------------------------------------------------------
*  0 Altera                    EPM3064A             1        SAMPLE/PRELOAD       BSR

jtag> get signal IO2
IO2 = 1
jtag> get signal IO3
IO3 = 1
jtag> get signal IO43
IO43 = 1
jtag> get signal IO44
IO44 = 1

# toggle single pin

jtag> instruction EXTEST
jtag> shift ir

jtag> print chain
 No. Manufacturer              Part                 Stepping Instruction          Register
-------------------------------------------------------------------------------------------------------------------
*  0 Altera                    EPM3064A             1        EXTEST               BSR

jtag> set signal IO10 out 0
jtag> shift dr

# re-read values of all pins

jtag> instruction SAMPLE/PRELOAD
jtag> shift ir
jtag> shift dr
jtag> get signal IO10
IO10 = 0

SVF programming

jtag> svf /blue-zfs/FPGA/Altera-x300/x300_dongle/output_files/dongle1.svf stop progress
detail: Parsing     20/520 (  3%)warning: unimplemented mode 'ABSENT' for TRST
detail: Parsing    520/520 (100%)detail: 
detail: Scanned device output matched expected TDO values.

VHDL to toggle pins

Toggle pins on all four sides of CPLD and create additional two images with all one and all zero for easy test where pin is

Then I connected logic analyzer on pins and tried different svf files (all-0, all-1, left, bottom, right, top) to locate which pin change depending on image loaded. To isolate pins I used EXTEST and toggled pins.

RJ45

PS2

PS2

http://www.computer-engineering.org/ps2protocol/

female socket	male plug

6-pin Mini-DIN (PS/2):
1 - Data
2 - Not Implemented
3 - Ground
4 - Vcc (+5V)
5 - Clock
6 - Not Implemented

Keyboard (left, purple)

Mouse (right, green)

Audio jack

R2R D2A

all measurements are done on Hantek 2090 with 500mV/div setting which may account for some accuracy errors

channel 1

channel 2

Bunch of references for Altera FPGA

JTAG pinout

Bus Pirate programming

• http://dangerousprototypes.com/forum/viewtopic.php?f=4&t=2505

The Bus Pirate can program CPLDs and FPGAs using XSVF format bitstreams and XSVF player firmware. Altera might not output XSVF directly, but there is a simple converter for SVF to XSVF.

Windows binaries are provided, but the source should also compile under Linux. Source is in the Bus Pirate SVN:
https://code.google.com/p/the-bus-pirate/source/browse/#svn%2Ftrunk%2Fscripts%2FXSVF

Bus Pirate FPGA and CPLD programming with XSVF:
http://dangerousprototypes.com/docs/Bus_Pirate#FPGA_and_CPLD_programming

SVF to XSVF converter:
http://dangerousprototypes.com/docs/JTAG_SVF_to_XSVF_file_converter

USB Blaster

FX2LP firmware

• libusb tools https://github.com/swetland/jtag

• https://github.com/mithro/ixo-usb-jtag usb-jtag - Altera USB Blaster Emulation with a FX2

• https://github.com/binary-logic/vj-uart - serial over JTAG USB Blaster for Cyclone IV

Quartus

Create SVF file

http://www.altera.com/support/kdb/solutions/rd07222008_677.html

To generate an SVF file in Quartus® II software, follow the steps below:

• Open the Quartus II programmer and add a .sof / .pof file into the programmer window.
• Select the File Menu then select Create/Update within this menu choose Create JAM, SVF, or ISC File.
• Input a file name for your SVF file output.
• In the File Format drop-down select Serial Vector File (SVF) as your output file type.
• Press ok to generate your SVF file.

manual pin assigment

edit .*qsf file and add:

set_location_assignment PIN_AP30 -to qdr_q[35]

13.0sp1 start

dpavlin@klin:~$ /opt/altera/13.0sp1/quartus/bin/quartus --64bit

Altera hardware

• X300 dongle
• X300 PCI
• MiniPCIe/PCI/LPC Combo-Debug Card

References

• http://embeddedprogrammer.blogspot.com/2012/07/hacking-ov7670-camera-module-sccb-cheat.html

RaspberryPi

• http://nicolasfley.fast-page.org/?page_id=35

FPGA

• http://hamsterworks.co.nz/mediawiki/index.php/OV7670_camera
• https://github.com/ahmadabbas55/miniOV7670

Stereo vision

• http://danstrother.com/2011/06/10/fpga-stereo-vision-core-released/
• http://code.danstrother.com/dls_cores/

dpavlin@blue:/bluez/FPGA/ULX2S/uk101$ KERNEL[16887.354856] add      /devices/pci0000:00/0000:00:1a.0/usb3/3-1/3-1.1/3-1.1.3 (usb)
KERNEL[16887.358543] add      /devices/pci0000:00/0000:00:1a.0/usb3/3-1/3-1.1/3-1.1.3/3-1.1.3:1.0 (usb)
UDEV  [16887.365476] add      /devices/pci0000:00/0000:00:1a.0/usb3/3-1/3-1.1/3-1.1.3 (usb)
KERNEL[16888.370326] add      /module/usbserial (module)
KERNEL[16888.370344] add      /bus/usb-serial (bus)
KERNEL[16888.370378] add      /bus/usb/drivers/usbserial (drivers)
KERNEL[16888.370396] add      /bus/usb/drivers/usbserial_generic (drivers)
KERNEL[16888.370413] add      /bus/usb-serial/drivers/generic (drivers)
UDEV  [16888.370685] add      /module/usbserial (module)
UDEV  [16888.370725] add      /bus/usb-serial (bus)
UDEV  [16888.370879] add      /bus/usb/drivers/usbserial (drivers)
UDEV  [16888.370901] add      /bus/usb-serial/drivers/generic (drivers)
UDEV  [16888.370928] add      /bus/usb/drivers/usbserial_generic (drivers)
KERNEL[16888.371900] add      /module/ftdi_sio (module)
KERNEL[16888.371923] add      /bus/usb/drivers/ftdi_sio (drivers)
KERNEL[16888.371945] add      /bus/usb-serial/drivers/ftdi_sio (drivers)
UDEV  [16888.371980] add      /module/ftdi_sio (module)
UDEV  [16888.372050] add      /bus/usb-serial/drivers/ftdi_sio (drivers)
KERNEL[16888.372098] add      /devices/pci0000:00/0000:00:1a.0/usb3/3-1/3-1.1/3-1.1.3/3-1.1.3:1.0/ttyUSB0 (usb-serial)
UDEV  [16888.372124] add      /bus/usb/drivers/ftdi_sio (drivers)
KERNEL[16888.372401] add      /devices/pci0000:00/0000:00:1a.0/usb3/3-1/3-1.1/3-1.1.3/3-1.1.3:1.0/ttyUSB0/tty/ttyUSB0 (tty)
UDEV  [16888.372546] add      /devices/pci0000:00/0000:00:1a.0/usb3/3-1/3-1.1/3-1.1.3/3-1.1.3:1.0 (usb)
UDEV  [16888.372888] add      /devices/pci0000:00/0000:00:1a.0/usb3/3-1/3-1.1/3-1.1.3/3-1.1.3:1.0/ttyUSB0 (usb-serial)
UDEV  [16888.374650] add      /devices/pci0000:00/0000:00:1a.0/usb3/3-1/3-1.1/3-1.1.3/3-1.1.3:1.0/ttyUSB0/tty/ttyUSB0 (tty)
KERNEL[16929.333395] add      /devices/pci0000:00/0000:00:1a.0/usb3/3-1/3-1.6/3-1.6.3 (usb)
KERNEL[16929.333629] add      /devices/pci0000:00/0000:00:1a.0/usb3/3-1/3-1.6/3-1.6.3/3-1.6.3:1.0 (usb)
UDEV  [16929.338304] add      /devices/pci0000:00/0000:00:1a.0/usb3/3-1/3-1.6/3-1.6.3 (usb)
UDEV  [16929.338759] add      /devices/pci0000:00/0000:00:1a.0/usb3/3-1/3-1.6/3-1.6.3/3-1.6.3:1.0 (usb)
KERNEL[16929.708966] add      /devices/pci0000:00/0000:00:1a.0/usb3/3-1/3-1.6/3-1.6.3/3-1.6.3.2 (usb)
KERNEL[16929.712382] add      /devices/pci0000:00/0000:00:1a.0/usb3/3-1/3-1.6/3-1.6.3/3-1.6.3.2/3-1.6.3.2:1.0 (usb)
KERNEL[16929.712433] add      /devices/pci0000:00/0000:00:1a.0/usb3/3-1/3-1.6/3-1.6.3/3-1.6.3.2/3-1.6.3.2:1.0/media0 (media)
KERNEL[16929.773679] add      /devices/pci0000:00/0000:00:1a.0/usb3/3-1/3-1.6/3-1.6.3/3-1.6.3.2/3-1.6.3.2:1.0/video4linux/video0 (video4linux)
KERNEL[16929.773733] add      /devices/pci0000:00/0000:00:1a.0/usb3/3-1/3-1.6/3-1.6.3/3-1.6.3.2/3-1.6.3.2:1.0/input/input30 (input)
KERNEL[16929.773790] add      /devices/pci0000:00/0000:00:1a.0/usb3/3-1/3-1.6/3-1.6.3/3-1.6.3.2/3-1.6.3.2:1.0/input/input30/event16 (input)
KERNEL[16929.773883] add      /devices/pci0000:00/0000:00:1a.0/usb3/3-1/3-1.6/3-1.6.3/3-1.6.3.2/3-1.6.3.2:1.1 (usb)
KERNEL[16929.942458] add      /devices/pci0000:00/0000:00:1a.0/usb3/3-1/3-1.6/3-1.6.3/3-1.6.3.3 (usb)
KERNEL[16929.943007] add      /devices/pci0000:00/0000:00:1a.0/usb3/3-1/3-1.6/3-1.6.3/3-1.6.3.3/3-1.6.3.3:1.0 (usb)
KERNEL[16929.943064] add      /devices/pci0000:00/0000:00:1a.0/usb3/3-1/3-1.6/3-1.6.3/3-1.6.3.3/3-1.6.3.3:1.0/video4linux/video2 (video4linux)
UDEV  [16929.949326] add      /devices/pci0000:00/0000:00:1a.0/usb3/3-1/3-1.6/3-1.6.3/3-1.6.3.2 (usb)
UDEV  [16929.949933] add      /devices/pci0000:00/0000:00:1a.0/usb3/3-1/3-1.6/3-1.6.3/3-1.6.3.2/3-1.6.3.2:1.1 (usb)
UDEV  [16929.949946] add      /devices/pci0000:00/0000:00:1a.0/usb3/3-1/3-1.6/3-1.6.3/3-1.6.3.2/3-1.6.3.2:1.0 (usb)
UDEV  [16929.950176] add      /devices/pci0000:00/0000:00:1a.0/usb3/3-1/3-1.6/3-1.6.3/3-1.6.3.3 (usb)
UDEV  [16929.950550] add      /devices/pci0000:00/0000:00:1a.0/usb3/3-1/3-1.6/3-1.6.3/3-1.6.3.2/3-1.6.3.2:1.0/media0 (media)
UDEV  [16929.950861] add      /devices/pci0000:00/0000:00:1a.0/usb3/3-1/3-1.6/3-1.6.3/3-1.6.3.2/3-1.6.3.2:1.0/input/input30 (input)
UDEV  [16929.951576] add      /devices/pci0000:00/0000:00:1a.0/usb3/3-1/3-1.6/3-1.6.3/3-1.6.3.2/3-1.6.3.2:1.0/input/input30/event16 (input)
UDEV  [16929.952469] add      /devices/pci0000:00/0000:00:1a.0/usb3/3-1/3-1.6/3-1.6.3/3-1.6.3.2/3-1.6.3.2:1.0/video4linux/video0 (video4linux)
UDEV  [16930.953075] add      /devices/pci0000:00/0000:00:1a.0/usb3/3-1/3-1.6/3-1.6.3/3-1.6.3.3/3-1.6.3.3:1.0 (usb)
UDEV  [16930.954337] add      /devices/pci0000:00/0000:00:1a.0/usb3/3-1/3-1.6/3-1.6.3/3-1.6.3.3/3-1.6.3.3:1.0/video4linux/video2 (video4linux)

dpavlin@blue:/bluez/FPGA/ULX2S/uk101$ 
dpavlin@blue:/bluez/FPGA/ULX2S/uk101$ ../ujprog-x86-64 ./uk101-ulx2s8k.jed 
ULX2S JTAG programmer v 1.07 $Id: ujprog.c 1748 2014-01-09 15:07:43Z marko $
KERNEL[17115.768270] remove   /devices/pci0000:00/0000:00:1a.0/usb3/3-1/3-1.1/3-1.1.3/3-1.1.3:1.0/ttyUSB0/tty/ttyUSB0 (tty)
KERNEL[17115.768305] remove   /devices/pci0000:00/0000:00:1a.0/usb3/3-1/3-1.1/3-1.1.3/3-1.1.3:1.0/ttyUSB0 (usb-serial)
Using USB JTAG cable.
UDEV  [17115.769313] remove   /devices/pci0000:00/0000:00:1a.0/usb3/3-1/3-1.1/3-1.1.3/3-1.1.3:1.0/ttyUSB0/tty/ttyUSB0 (tty)
UDEV  [17115.769664] remove   /devices/pci0000:00/0000:00:1a.0/usb3/3-1/3-1.1/3-1.1.3/3-1.1.3:1.0/ttyUSB0 (usb-serial)
Programming: 100%  
Completed in 5.88 seconds.
dpavlin@blue:/bluez/FPGA/ULX2S/uk101$ 

loader

https://github.com/GadgetFactory/Papilio-Loader/pull/6

dpavlin@blue:/blue-zfs/FPGA/Papilio$ git clone https://github.com/GadgetFactory/Papilio-Loader.git
dpavlin@blue:/blue-zfs/FPGA/Papilio$ cd Papilio-Loader/papilio-prog
dpavlin@blue:/blue-zfs/FPGA/Papilio/Papilio-Loader/papilio-prog$ git checkout -b revert-libftdi2 261d0dd02f5489c63e8227c6f916af5efacfbe7a
dpavlin@blue:/blue-zfs/FPGA/Papilio/Papilio-Loader/papilio-prog$ ./autogen.sh 
dpavlin@blue:/blue-zfs/FPGA/Papilio/Papilio-Loader/papilio-prog$ ./configure && make

# check compiled binary
dpavlin@blue:/blue-zfs/FPGA/Papilio/Papilio-Loader/papilio-prog$ ./papilio-prog -v -j
Using built-in device list
JTAG chainpos: 0 Device IDCODE = 0x24001093     Desc: XC6SLX9
USB transactions: Write 3 read 2 retries 1

ZAP IDE

compilation

dpavlin@blue:/blue-zfs/FPGA/Papilio$ git clone https://github.com/GadgetFactory/ZAP--ZPUino-Arduino-Papilio--IDE.git

dpavlin@blue:/blue-zfs/FPGA/Papilio$ cd ZAP--ZPUino-Arduino-Papilio--IDE/build/
dpavlin@blue:/blue-zfs/FPGA/Papilio/ZAP--ZPUino-Arduino-Papilio--IDE/build$ ant

dpavlin@blue:/blue-zfs/FPGA/Papilio/ZAP--ZPUino-Arduino-Papilio--IDE/build/linux$ ln -s zpu_tools_linux32.tar.bz2 zpu_tools_linux64.tar.bz2 

fix papilio-prog to use Linux binary

dpavlin@blue:/blue-zfs/FPGA/Papilio/ZAP--ZPUino-Arduino-Papilio--IDE/build/linux/work$ vi ./hardware/zpuino/zpu/platform.txt

# fix papilioprog to papilio-prog
tools.papilioprog.cmd=papilio-prog

# remove .exe from this line
tools.papilioprog.erase.pattern="{path}/bin/papilio-prog" -c


dpavlin@blue:/blue-zfs/FPGA/Papilio/ZAP--ZPUino-Arduino-Papilio--IDE/build/linux/work$ chmod 755 hardware/tools/papilio/papilio_loader/Papilio_Programmer.sh 


# copy compiled papilio-prog to correct location and fix permissions
dpavlin@blue:/blue-zfs/FPGA/Papilio/ZAP--ZPUino-Arduino-Papilio--IDE/build/linux/work$ cp ../../../../Papilio-Loader/papilio-prog/papilio-prog hardware/tools/papilio/papilio_loader/bin/
dpavlin@blue:/blue-zfs/FPGA/Papilio/ZAP--ZPUino-Arduino-Papilio--IDE/build/linux/work$ chmod 755 hardware/tools/papilio/papilio_loader/bin/papilio-prog

running IDE

Run arduino GUI:

dpavlin@blue:/blue-zfs/FPGA/Papilio/ZAP--ZPUino-Arduino-Papilio--IDE/build/linux/work$ ./arduino

Compilation works, but programming doesn't with error:

Board: Unknown board @ 96000000 Hz (0xa4041700)

so, let's rebuild zpuprogrammer

http://forum.gadgetfactory.net/index.php?/topic/1588-how-to-program-the-arduino-sketch-for-zpuino-to-the-spi-flash/page-2#entry11242

dpavlin@blue:/blue-zfs/ZPUino/ZPUino-HDL/zpu/hdl/zpuino/programmer$ git remote -v
origin  https://github.com/alvieboy/ZPUino-HDL/ (fetch)
origin  https://github.com/alvieboy/ZPUino-HDL/ (push)

dpavlin@blue:/blue-zfs/ZPUino/ZPUino-HDL/zpu/hdl/zpuino/programmer$ autoreconf --install
dpavlin@blue:/blue-zfs/ZPUino/ZPUino-HDL/zpu/hdl/zpuino/programmer$ ./configure
dpavlin@blue:/blue-zfs/ZPUino/ZPUino-HDL/zpu/hdl/zpuino/programmer$ make
dpavlin@blue:/blue-zfs/ZPUino/ZPUino-HDL/zpu/hdl/zpuino/programmer$ cp zpuinoprogrammer /blue-zfs/FPGA/Papilio/ZAP--ZPUino-Arduino-Papilio--IDE/build/linux/dist/tools/
# this one is for already built version
dpavlin@blue:/blue-zfs/ZPUino/ZPUino-HDL/zpu/hdl/zpuino/programmer$ cp zpuinoprogrammer /blue-zfs/FPGA/Papilio/ZAP--ZPUino-Arduino-Papilio--IDE/build/linux/work/hardware/tools/zpu/bin/zpuinoprogrammer

program boot file (IDE doesn't have permission to do so)

dpavlin@blue:/blue-zfs/FPGA/Papilio$ ./papilio-prog -v -f ./zap-2.0.5/hardware/zpuino/zpu/bootloaders/lx9/zpuino-1.0-PapilioPro-S6LX9-RetroCade-1.0.bit
Using built-in device list
JTAG chainpos: 0 Device IDCODE = 0x24001093     Desc: XC6SLX9
Created from NCD file: papilio_pro_routed.ncd;UserID=0xFFFFFFFF
Target device: 6slx9tqg144
Created: 2012/11/20 00:16:43
Bitstream length: 2727072 bits

Uploading "./zap-2.0.5/hardware/zpuino/zpu/bootloaders/lx9/zpuino-1.0-PapilioPro-S6LX9-RetroCade-1.0.bit". DNA is 0x190efd25eb57c9fe
Done.
Programming time 549.2 ms
USB transactions: Write 176 read 8 retries 5

run IDE

dpavlin@blue:/blue-zfs/FPGA/Papilio/ZAP--ZPUino-Arduino-Papilio--IDE/build/linux/work$ ./arduino
Experimental:  JNI_OnLoad called.
Stable Library
=========================================
Native lib Version = RXTX-2.1-7
Java lib Version   = RXTX-2.1-7

verification will fail, so just upload sketch:

dpavlin@blue:/blue-zfs/FPGA/Papilio/Papilio-SOC/zpu/hdl/zpuino/programmer$ ./zpuinoprogrammer -s 1000000 -R -d /dev/ttyUSB1 -b /tmp/build383944339812357036.tmp/Autoscroll.cpp.bin -U
Board: GadgetFactory Papilio Pro LX9 @ 96000000 Hz (0xa4041700)
Upload completed successfully in 0.05 seconds.

zpugcc

dpavlin@blue:/blue-zfs/FPGA/Papilio$ git clone git://repo.or.cz/zpugcc.git
Cloning into 'zpugcc'...
remote: Counting objects: 35519, done.
remote: Compressing objects: 100% (26110/26110), done.
remote: Total 35519 (delta 8445), reused 35519 (delta 8445)
Receiving objects: 100% (35519/35519), 70.18 MiB | 426.00 KiB/s, done.
Resolving deltas: 100% (8445/8445), done.
Checking connectivity... done.
Checking out files: 100% (35311/35311), done.
dpavlin@blue:/blue-zfs/FPGA/Papilio$ cd zpugcc/toolchain
dpavlin@blue:/blue-zfs/FPGA/Papilio/zpugcc/toolchain$ git diff build.sh
diff --git a/toolchain/build.sh b/toolchain/build.sh
index 783beaa..034929c 100644
--- a/toolchain/build.sh
+++ b/toolchain/build.sh
@@ -3,6 +3,9 @@ set -e
 rm -rf build
 mkdir build
 cd build
+mkdir bin
+ln -s /bin/true bin/makeinfo
+export PATH=`pwd`/bin:$PATH
 ../binutils/configure --target=zpu-elf --prefix=`pwd`/../install
 make
 make install
dpavlin@blue:/blue-zfs/FPGA/Papilio/zpugcc/toolchain$ sh -x build.sh

RetroCade MegaWing

http://retrocade.gadgetfactory.net/index.php?n=Main.RetroCadeMegaWing

LCD

Modify Examples/LiqueidCrystal/Autoscroll

// initialize the library with the numbers of the interface pins
LiquidCrystal lcd(26, 24, 23, 22, 21, 20);

void setup() {
  // contrast to GND
  pinMode(46, OUTPUT);
  digitalWrite(46, LOW);
  // RW to ground
  pinMode(25, OUTPUT);
  digitalWrite(25, LOW);

  // set up the LCD's number of columns and rows: 
  lcd.begin(16,2);
}

ZPU (without Arduino IDE)

• http://forum.gadgetfactory.net/index.php?/topic/1863-bare-metal-zpu-hello-world/

Xilinx Virtual Cable Daemon

• https://github.com/tmbinc/xvcd/tree/ftdi