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Dobrica Pavlinušić's random unstructured stuff
ULX3S: Revision 61
first stepsHere I will try to document correct order to read documentation to get setup for ULX3S: https://github.com/emard/ulx3s-bin/blob/master/README.md udev ruleujproggit clone https://github.com/f32c/tools f32c-tools cd f32c-tools/ujprog/ dpavlin@x200:/mnt/nuc/FPGA/f32c-tools/ujprog$ rm ujprog dpavlin@x200:/mnt/nuc/FPGA/f32c-tools/ujprog$ make -f Makefile.linux cc -Wall -D__linux__ -std=gnu99 -static ujprog.c /usr/lib/x86_64-linux-gnu/libftdi.a /usr/lib/x86_64-linux-gnu/libusb.a -o ujprog dpavlin@x200:/mnt/nuc/FPGA/f32c-tools/ujprog$ sudo cp ujprog /usr/local/bin/
passthru to access esp32source at https://github.com/emard/ulx3s-passthru dpavlin@x200:/mnt/nuc/FPGA/ulx3s-bin/fpga/passthru/passthru-v20-85f$ ujprog -j flash ulx3s_85f_passthru.bit ULX2S / ULX3S JTAG programmer v 3.0.92 (built Nov 19 2019 10:55:50) Using USB cable: ULX3S FPGA 12K v3.0.3 [Wed Nov 20 18:02:01 2019] ftdi_sio ttyUSB0: FTDI USB Serial Device converter now disconnected from ttyUSB0 [Wed Nov 20 18:02:01 2019] ftdi_sio 1-5.2:1.0: device disconnected Programming: 100% Completed in 24.36 seconds. [Wed Nov 20 18:02:25 2019] usb 1-5.2: reset full-speed USB device number 56 using ehci-pci [Wed Nov 20 18:02:26 2019] ftdi_sio 1-5.2:1.0: FTDI USB Serial Device converter detected [Wed Nov 20 18:02:26 2019] usb 1-5.2: Detected FT-X [Wed Nov 20 18:02:26 2019] usb 1-5.2: FTDI USB Serial Device converter now attached to ttyUSB0 update size of your FPGAdpavlin@x200:/mnt/nuc/FPGA/ulx3s-bin$ usb-jtag/linux-amd64/ftx_prog --product "ULX3S FPGA 85K v3.0.3" power cycle board to get new usb id, test that it's supported by ujprog dpavlin@x200:/mnt/nuc/FPGA/ulx3s-bin$ ujprog -r esptool and esp32 booting problemsYou should be using ecptool from ulx3s-bin repository to quite @emard from https://gitter.im/ulx3s/Lobby#dark-theme OK then. If you have issues with ESP32 not booting with SD card but booting without SD card then then the fuse burn script from ulx3s-bin should be run. So far so good, you erased its flash, try linux. If no issue then can try to flash micropython and my new ESP32 OTA programmer ecp5.py end uftpd.py I have wisely taken some esptool.py which works and frozen it in ulx3s, versions change all the time and maybe you took something in the middle of development action :) install micropythonhttps://github.com/emard/esp32ecp5/ dpavlin@nuc:/nuc/FPGA$ git clone https://github.com/emard/esp32ecp5/ dpavlin@nuc:/nuc/FPGA$ cd esp32ecp5/ dpavlin@x200:/mnt/nuc/FPGA/esp32ecp5$ wget https://micropython.org/resources/firmware/esp32-idf3-20191120-v1.11-580-g973f68780.bin It's important to erase flash or micropyhton will complain about corrupt fat filesystem like:
FAT filesystem appears to be corrupted. If you had important data there, you
dpavlin@x200:/mnt/nuc/FPGA/esp32ecp5$ ../ulx3s-bin/esp32/serial-uploader/esptool.py --chip esp32 --port /dev/ttyUSB0 erase_flash
esptool.py v2.6-beta1
Serial port /dev/ttyUSB0
Connecting....
Chip is ESP32D0WDQ6 (revision 1)
Features: WiFi, BT, Dual Core, 240MHz, VRef calibration in efuse, Coding Scheme None
MAC: a4:cf:12:55:c5:60
Uploading stub...
Running stub...
Stub running...
Erasing flash (this may take a while)...
Chip erase completed successfully in 8.7s
Hard resetting via RTS pin...
dpavlin@x200:/mnt/nuc/FPGA/esp32ecp5$ ../ulx3s-bin/esp32/serial-uploader/esptool.py --chip esp32 --port /dev/ttyUSB0 --baud 460800 write_flash -z 0x1000 esp32-idf3-20191120-v1.11-580-g973f68780.bin
esptool.py v2.6-beta1
Serial port /dev/ttyUSB0
Connecting....
Chip is ESP32D0WDQ6 (revision 1)
Features: WiFi, BT, Dual Core, 240MHz, VRef calibration in efuse, Coding Scheme None
MAC: a4:cf:12:55:c5:60
Uploading stub...
Running stub...
Stub running...
Changing baud rate to 460800
Changed.
Configuring flash size...
Auto-detected Flash size: 4MB
Compressed 1240192 bytes to 783187...
Wrote 1240192 bytes (783187 compressed) at 0x00001000 in 18.7 seconds (effective 529.3 kbit/s)...
Hash of data verified.
Leaving...
Hard resetting via RTS pin...
dpavlin@x200:/mnt/nuc/FPGA/esp32ecp5$ microcom -p /dev/ttyUSB0
connected to /dev/ttyUSB0
Escape character: Ctrl-\
Type the escape character to get to the prompt.
>>>
> help()
Welcome to MicroPython on the ESP32!
For generic online docs please visit http://docs.micropython.org/
For access to the hardware use the 'machine' module:
import machine
pin12 = machine.Pin(12, machine.Pin.OUT)
pin12.value(1)
pin13 = machine.Pin(13, machine.Pin.IN, machine.Pin.PULL_UP)
print(pin13.value())
i2c = machine.I2C(scl=machine.Pin(21), sda=machine.Pin(22))
i2c.scan()
i2c.writeto(addr, b'1234')
i2c.readfrom(addr, 4)
Basic WiFi configuration:
import network
sta_if = network.WLAN(network.STA_IF); sta_if.active(True)
sta_if.scan() # Scan for available access points
sta_if.connect("<AP_name>", "<password>") # Connect to an AP
sta_if.isconnected() # Check for successful connection
Control commands:
CTRL-A -- on a blank line, enter raw REPL mode
CTRL-B -- on a blank line, enter normal REPL mode
CTRL-C -- interrupt a running program
CTRL-D -- on a blank line, do a soft reset of the board
CTRL-E -- on a blank line, enter paste mode
For further help on a specific object, type help(obj)
For a list of available modules, type help('modules')
webrepldpavlin@klin:/klin/FPGA$ git clone https://github.com/hyperglitch/webrepl You can send files from command-line: dpavlin@x200:/mnt/nuc/FPGA/webrepl$ ./webrepl_cli.py -p ulx3s ../esp32ecp5/ecp5.py 192.168.3.130:/ op:put, host:192.168.3.130, port:8266, passwd:ulx3s. ../esp32ecp5/ecp5.py -> /ecp5.py Remote WebREPL version: (1, 11, 0) Sent 22777 of 22777 bytes dpavlin@x200:/mnt/nuc/FPGA/webrepl$ ./webrepl_cli.py -p ulx3s ../esp32ecp5/uftpd.py 192.168.3.130:/ op:put, host:192.168.3.130, port:8266, passwd:ulx3s. ../esp32ecp5/uftpd.py -> /uftpd.py Remote WebREPL version: (1, 11, 0) Sent 19482 of 19482 bytes open source toolchainJust use kost's binary builds: https://github.com/alpin3/ulx3s/releases this is old and needs update dpavlin@klin:/klin/FPGA$ git clone https://github.com/SymbiFlow/prjtrellis dpavlin@klin:/klin/FPGA/prjtrellis$ ./download-latest-db.sh dpavlin@klin:/klin/FPGA/prjtrellis$ cd libtrellis/ dpavlin@klin:/klin/FPGA/prjtrellis/libtrellis$ sudo apt-get install libpython3-dev libboost-python-dev libboost-filesystem-dev libboost-thread-dev libboost-program-options-dev dpavlin@klin:/klin/FPGA/prjtrellis/libtrellis$ cmake -DCMAKE_INSTALL_PREFIX=/usr/local . dpavlin@klin:/klin/FPGA/prjtrellis/libtrellis$ make sudo make install dpavlin@klin:/klin/FPGA/nextpnr$ cmake -DARCH=ecp5 -DBUILD_GUI=OFF -DTRELLIS_ROOT=../prjtrellis/ . make make install diamondhttps://github.com/jandob/lattice-diamond-archlinux/blob/master/eth0DummyToggle dockerhttps://gitter.im/ulx3s/Lobby?at=5dff4b08d2dadb38935c570a https://github.com/dok3r/diamond/ docker run -it -v /host/fpga:/fpga -- local /host/fpga will end up in /fpga in docker yes path will be fine you will be missing make so inside container you need to yum install make and yum install libxslt export ETHMAC=b0:5a:da:XX:XX:XX set your MAC docker run -it -v /media/internal/FPGA:/fpga -e LM_LICENSE_FILE=/fpga/license.dat --mac-address=$ETHMAC --privileged --ipc host -v /dev/bus/usb/:/dev/bus/usb/ dok3r/diamond:latest run docker yum install make libxslt go tu project inside fpga folder and find makefile for diamond and then just make then you share it with docker container with -v /yourHOSTfpgadir:/fpgadockerdir -e LM_LICENSE_FILE=/fpgadockerdir for version you need to use like this dok3r/diamond:version versions are here https://hub.docker.com/r/dok3r/diamond/tags docker run -it -v /media/internal/FPGA:/fpga -e LM_LICENSE_FILE=/fpga/license.dat --mac-address=$ETHMAC --privileged --ipc host -v /dev/bus/usb/:/dev/bus/usb/ dok3r/diamond:v3.7 like this Not understanding -v /media/internal/FPGA that is my local FPGA folder with samples and license.dat it will mount on docker /fpga and I see now that I need to share prjtrallis folder to docker so it can do ecppll docker run -it -v /media/internal/FPGA:/fpga -v /local/prjtrellis/libtrellis:/mt/scratch/tmp/openfpga/prjtrellis/libtrellis -e LM_LICENSE_FILE=/fpga/license.dat --mac-address=$ETHMAC --privileged --ipc host -v /dev/bus/usb/:/dev/bus/usb/ dok3r/diamond:v3.7 but for that we will need @kost we probably need ecppll and tools already there and compiled with centos- maybe just binaries NEShttps://gitter.im/ulx3s/Lobby?at=5de033f49319bb5190a9c3b6
oberonhttps://gitter.im/ulx3s/Lobby?at=5e007d1e8897197969e3331c
So, I have now managed to build oberon with diamond 3.7.
1. Build it with diamond 3.11, which fails
Thanks @kost for adding for adding make and libxslt to the docker image. It would be useful if you could patch the platform_check to allow versions before 3.11 to run on 5.* linux. docker pull dok3r/diamond:v3.7
woohoo! Cool
case $VERSION in It needs:
case $VERSION in
I did the docker pull to make sure I had the latest version. 21f repack from 25f imageecpunpack --input ulx3s_25.bit --textcfg ulx3s_12f.config --idcode 0x41111043 ecppack --input ulx3s_12f.config --bit ulxs3_12f.bit --idcode 0x21111043 compress bitstreamecppack --compress esp32ps2https://github.com/emard/esp32ps2 saxonsoclinux
Instructions at https://github.com/lawrie/saxonsoc-ulx3s-bin/tree/master/linux https://gitter.im/ulx3s/Lobby?at=5de8ba2f08d0c961b7f3a25f git clone https://github.com/SpinalHDL/buildroot.git -b saxon buildroot git clone https://github.com/SpinalHDL/linux.git -b vexriscv --depth 1 linux cd buildroot cp board/spinal/saxon_default/linux_nonet.config board/spinal/saxon_default/linux.config # Add extra options to board/spinal/saxon_default/linux.config make spinal_saxon_default_defconfig make linux-rebuild all -j$(nproc) output/host/bin/riscv32-linux-objcopy -O binary output/images/vmlinux output/images/Image # Make sure Image is at least 116KB less than 4MB 85f versionhttps://gitter.im/ulx3s/Lobby?at=5dea74995ac7f22fb57055ae https://github.com/lawrie/saxonsoc-ulx3s-bin/blob/master/linux/README.md https://github.com/lawrie/saxonsoc-ulx3s-bin/tree/master/linux/u-boot https://github.com/SpinalHDL/SaxonSoc/tree/dev/bsp/Ulx3sLinuxUboot ledshttps://gitter.im/ulx3s/Lobby?at=5dec101f46397c721ca4c814 #!/bin/sh cd /sys/class/gpio echo 488 > export echo out > gpio488/direction for i in 1 0 1 0 1 0 do sleep 0.1 echo $i > gpio488/value done slirphttps://gitter.im/ulx3s/Lobby?at=5df1467d0616d6515e20d197 modificationshttps://gitter.im/ulx3s/Lobby?at=5dfced993e3f133894ca9b4b i2chttps://gitter.im/ulx3s/Lobby?at=5dfcf29acf771f7708ff69e9 It should not be that hard. I have i2c in SaxonSoc in other projects such as https://github.com/SpinalHDL/SaxonSoc/blob/dev/hardware/scala/saxon/board/blackice/BlackiceSocArduino.scala#L25 The generated board support packages include a generated dts, but it is not used yet and the simple i2c generator that I wrote does not generate the dts. There is a problem building SaxonSoc Linux, that some build randomly do not work. It seems to be something to do with SDRAM access. @Dolu1990 is about to redo the SDRAM access for the Ulx3s, which should make it more reliable and faster, as he plans to support double frequency access. There is a lot of information on the development of the u-boot version here , which might be useful to you - SpinalHDL/SaxonSoc#7 https://github.com/SpinalHDL/SaxonSoc/pull/7 I2c Linux support will also need a spinal.lib driver here - https://github.com/SpinalHDL/linux/tree/linux-5.0.y/drivers/i2c The terasic De1Soc version of SaxonSoc Linux has a dts entry for an led for disk access - https://github.com/SpinalHDL/buildroot/blob/saxon/board/spinal/saxon_default/spinal_saxon_default_de1_soc.dts#L194 We really need a better GPIO mapping for the Ulx3s. That might involve including adding a second gpio peripheral to the hardware (gpioB) and doing a better lpf file mapping to pins. It might mean increasing the niumbers of pins that support interrupts. It would be good to include access to the buttons and switches and to make it easy to add Pmods that need interrupt support like the enc28j60 one. u-boot config for 85f with 64M SDRAMModify bootcmd to include: load mmc 0:1 0x80000000 /boot/uImage load mmc 0:1 0x81EF0000 /boot/dtb fdt add 0x81EF0000 fdt memory 0x80000000 0x04000000 bootm 0x80000000 - 0x81EF0000 ppp networkingsmp supporthttps://gitter.im/ulx3s/Lobby?at=5f4ea80bd4f0f55ebbf6ec33 Lawrie Griffiths @lawrie Sep 01 21:59
The new SaxonSoc is now working on a 12F for me. Here are the instructions to build from source - https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.1/bsp/radiona/ulx3s/smp ov7670 pmodhttps://github.com/goran-mahovlic/fpga-odysseus/tree/master/projects/OV7670-HDMI pmod pin mapping: https://github.com/goran-mahovlic/fpga-odysseus/blob/master/projects/OV7670-HDMI/ulx3s.lpf#L335 SCCB Pullup Resistorsfrom https://github.com/westonb/OV7670-Verilog The SCCB interface for the camera requires pull up resistors. You need to solder 4.7K resistors from the SIOD and SIOC pins on the camera to the 3.3V supply. You can do this yourself or have the staff in the EDS help you. csihttps://twitter.com/mad_archer_/status/1231249513509261313 https://github.com/libv/fosdem-video-linux litex(just links, need to test it)
spiramhttps://gitter.im/ulx3s/Lobby?at=5ef22d4c54d7862dc4a42395 @Speccery thereis also commandline "spiram.py" for some low-level inspection, so to reset TI this works for me spiram.poke(0x100008,bytearray(0xFC)) and to read bytes spiram.peek(0,16) bytearray(b'\x83\xe0\x00$\x83\xc0\t\x00\x83\xc0\n\x920\xaa\x04`') ledftx_prog --cbus 3 DRIVE_0 # green OFF ftx_prog --cbus 3 SLEEP # green ON if enumerated This is active after power cycle micropython blue led>>> from machine import Pin >>> led=Pin(5,Pin.OUT) >>> led.on() # upali plavu >>> led.off() # ugasi plavu micropythonfrom upysh import * ecp5pllMario Hoffmann @hoffma_gitlab Aug 05 16:11 Hello, I wanted to have a 90 degree shifted clock. I was trying out the ecp5pll from @emard. I get it running and the clock adjustment seems to work, but somehow it does not get shifted for me. Is this currently not working with yosys and so forth, is there anything I have to take care of, or might it just be a bug on my side? Tried to search this chat a bit and just searched a bit on the internet but the things I found about it were quite old and not necessarily about my problem. Any ideas? I am using the vhdl version btw emard @emard Aug 05 16:59 There's some order of signals and small delays between them for dynamic shifting to work. https://github.com/emard/ulx3s-misc/blob/master/examples/sdram/memtest_mister/hdl/top/top_memtest.v#L73 here is module to control phase shifts by pressing of BTN for testing of SDRAM with variable phase shift of the clock to chip Mario Hoffmann @hoffma_gitlab Aug 05 17:01 alright, ill look at that. thanks Mario Hoffmann @hoffma_gitlab Aug 05 17:53 Oh nice it works. My thinking was just a bit wrong and there was a little bug too. Thanks emard @emard Aug 05 18:07 ecp5pll has possibility for fine-precision phase adjustment but this simple BTN module doesn't generate proper phaseloadreg signal https://github.com/emard/ulx3s-misc/blob/master/examples/sdram/memtest_mister/hdl/btn_ecp5pll_phase.v#L51 displayhttps://gitter.im/ulx3s/Lobby?at=5f3b7df7ee58011680b36cb0 emard @emard Aug 18 09:06 SSD1331 96x64 is full featured OLED beautiful contrast, but currently best buy is ST7789 1.3" 240x240 LCD less contrast but more pix and less $. Do not solder directly the display. Solder female 7-pin header and plug the display. Mechanical stabilization can be 3D printed https://github.com/emard/ulx3s/tree/master/box it will "work" properly only if whole box is printed. There is no problem with heat normally to FPGA but SSD1331 with wrong software commands can become hot to fry fingers and smoke, it happened to me once, colors faded and I just replaced display. Onboard USB-SERIAL can provide 2nd JTAG channel for openocd debugger of RISCV processor it will work but it will be VERY slow (for debug single step ok, but for transferring Mbps no). rtchttps://gitter.im/ulx3s/Lobby?at=5f3b86a1a8c178017657caf6 emard @emard Aug 18 09:43 Yes for RTC I first saw it "works" but after few reboots I found out that it resets to compile time or something. Core could consult onboard RTC using i2c and then set unix time integer counter which will continue ticking afterwards. For setting RTC we have esp32 and other options. Btw import ntptime; ntptime.settime() will set ESP32 localtime() from a pool of network NTP servers and then esp32 can initialize onboard RTC here I have played with this https://github.com/emard/ulx3s-misc/tree/master/examples/rtc/micropython-mcp7940n/esp32 https://gitter.im/ulx3s/Lobby?at=5f3dbb34750a2741302ea427 emard @emard Aug 20 01:52 @pnru_gitlab here is 8-bit master interface. I haven't tested it very simple by reading seconds and seems ok https://github.com/emard/ulx3s-misc/blob/master/examples/rtc/i2c_master/proj/hdl/i2c_master_8bit.v https://gitter.im/ulx3s/Lobby?at=5f3e2d1c07c30d132a9c4f58 emard @emard Aug 20 09:58 when we are at verilog, I have found on the net several i2c bidirectional bridges. Only one code worked at our board but it works only if compiled by diamond. trellis compiles but doesn't work. Can someone take a look what I have missed: bridge: https://github.com/emard/ulx3s-misc/blob/master/examples/rtc/micropython-mcp7940n/proj/hdl/i2c_bridge.v toplevel usage: https://github.com/emard/ulx3s-misc/blob/master/examples/rtc/micropython-mcp7940n/proj/top/top_i2c_bridge.v emard @emard Aug 20 22:04 for me it works for any gpdi_scl/sda PULLMODE=UP, DOWN, or NONE so it's not pull setting. I can prepare a bitstream and micropython to ulx3s-bin example that initializes the clock setting time from NTP emard @emard Aug 20 22:18 https://github.com/emard/ulx3s-bin/tree/master/esp32/micropython/rtc can you try this RTC esp32 example for NTP setting? >>> rtcdemo.mcp.time should advance seconds emard @emard Aug 21 00:04
RTC traffic also appears at GPDI connector (if there's i2c chip 3.3V->5V adapter soldered on board PCA9306D). Some monitors may hold i2c lines. Also gpdi connector can be used to monitor traffic if e.g. you have hdmi breakout board emard @emard Aug 21 00:09
UPS but we have problem there will be 2 RTC chips colliding address :) emard @emard Aug 21 18:14 I fixed i2c_bridge.v to work with both trellis and diamond. Paul Ruiz @pnru_gitlab Aug 21 23:35
Which way does the battery go? I think with the + side (cap) up and the - side (ribbed) to the PCB? emard @emard Aug 21 23:59
Battery goes + up (larger part of battery should be in contact with metallic holder soldered) - down (smaller part of battery in contact to big circular pad on the PCB scopeiohttps://gitter.im/ulx3s/Lobby?at=5f3c27ffa05e464346d2f6ea emard @emard Aug 18 21:11 @gkankanh MAX11125 is 1Msa/s total so e.g. if you use 4ch then each channel will be 0.25MSa/s per channel. For oscilloscope it, we have ready solution at hdl4fpga/ULX3S/scopeio you will see traces on monitor. For analysis, onboard USB-serial can do 3Mbps so it could be nearly useable. For faster ADC, yes 100 Mbit ethernet ETH8720 from ebay, module for 2.2$ and for example ebay's AN108 AD/DA module 32MSa/s input, 125MSa/s output https://www.ebay.com/itm/ADDA-Module-Data-Signal-Acquisition-High-speed-Directly-pluggable-connector-/253556250998 also scopeio supports it how to solder headershttps://gitter.im/ulx3s/Lobby?at=5f3cd88378f4a801801336cb emard @emard Aug 19 09:45 To have GP/GN not be swapped from "default" design, Either solder 90° FEMALE headers on top side of board (nice for PMODs directly) or straight 0° MALE pins down on bottom side of board. PMODs can also plug to other end of flat cable and pinout will be identical as if 90° was soldered onboard. nmingenhttps://gitter.im/ulx3s/Lobby?at=5f3cfbce8b8d4f633effcea7 Lawrie Griffiths @lawrie Aug 19 12:15
I am using Ubuntu 20.04, so I need to use pip3 not pip. (You can't get python2 pip on 20.04 easily).
from nmigen import *
from nmigen_boards.ulx3s import *
class Blinky(Elaboratable):
def elaborate(self, platform):
led = platform.request("led", 0)
timer = Signal(26)
m = Module()
m.d.sync += timer.eq(timer + 1)
m.d.comb += led.o.eq(timer[-1])
return m
if __name__ == "__main__":
platform = ULX3S_85F_Platform()
platform.build(Blinky(), do_program=True)
https://github.com/GuzTech/ulx3s-nmigen-examples https://github.com/greatscottgadgets/luna SDRAM memtesthttps://gitter.im/ulx3s/Lobby?at=5f4ea96249a1df0a12c0d83e Lawrie Griffiths @lawrie Sep 01 22:04
@pnru_gitlab @Dolu1990 asked these questions about using the SDRAM, which I thought you might know something about from all your recent work on SDRAM drivers: Dolu1990 @Dolu1990 Sep 01 22:05 Moaaaar powaaaaaaaa emard @emard Sep 01 22:36 oooh yeea :)) if you want to push SDRAM near the edge and give it some heat, on selected designs it can push 133MHz chips to 180-200 MHz, fmax depends on each board. 12F performs better than 85F. Here's memtest https://github.com/emard/ulx3s-misc/tree/master/examples/sdram/memtest_mister shows results on DVI monitor and with BTNs can adjust phase shift dynamically and watch for errors. Dolu1990 @Dolu1990 Sep 01 23:01
<3 emard @emard Sep 01 23:08 Yes this has a classic sdram driver that normally needs 90° phase offset to chip hardware, but as fmax is getting higher the actual phase shift which makes it really work moves. PLL is used to provide phase shift. Paul has made a better sdram driver with cool vendor-independent delay solution with a number of NOT gates.Only ns delay per NOT gate remains vendor dependent Dolu1990 @Dolu1990 Sep 01 23:09 ok :D Paul Ruiz @pnru_gitlab 00:02
@lawrie @Dolu1990 I am not sure I understand the SDRAM questions. In any case, my latest version is here: https://gitlab.com/pnru/cortex/-/blob/master/sdram.v I am not sure what you mean by "using DDR io" - does the SDRAM chip on the ULX3S support DDR? Maybe you mean by DDR that it runs at twice the speed of the CPU or that it uses burst size 2? I don't know what the critical path in the SDRAM chip is, but I do have a hypothesis. When working with a CAS delay of 3 clocks, the data really arrives after 2 clocks plus 6-7ns (spending on the speed grade). If you clock a grade 6 chip (PC166) faster, a clock cycle will take less than 6ns and the data will only arrive after the third rising clock edge. My guess is that the 6-7ns is related to the speed of the sense amplifiers or something like that. TODOtry various projects for ulx3s |