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Helpful notes from chat about ULX3S



i2c

https://gitter.im/ulx3s/Lobby?at=5dfcf29acf771f7708ff69e9

It should not be that hard. I have i2c in SaxonSoc in other projects such as https://github.com/SpinalHDL/SaxonSoc/blob/dev/hardware/scala/saxon/board/blackice/BlackiceSocArduino.scala#L25

The generated board support packages include a generated dts, but it is not used yet and the simple i2c generator that I wrote does not generate the dts.

There is a problem building SaxonSoc Linux, that some build randomly do not work. It seems to be something to do with SDRAM access.

@Dolu1990 is about to redo the SDRAM access for the Ulx3s, which should make it more reliable and faster, as he plans to support double frequency access.

There is a lot of information on the development of the u-boot version here , which might be useful to you - SpinalHDL/SaxonSoc#7

https://github.com/SpinalHDL/SaxonSoc/pull/7

I2c Linux support will also need a spinal.lib driver here - https://github.com/SpinalHDL/linux/tree/linux-5.0.y/drivers/i2c

The terasic De1Soc version of SaxonSoc Linux has a dts entry for an led for disk access - https://github.com/SpinalHDL/buildroot/blob/saxon/board/spinal/saxon_default/spinal_saxon_default_de1_soc.dts#L194

We really need a better GPIO mapping for the Ulx3s. That might involve including adding a second gpio peripheral to the hardware (gpioB) and doing a better lpf file mapping to pins. It might mean increasing the niumbers of pins that support interrupts. It would be good to include access to the buttons and switches and to make it easy to add Pmods that need interrupt support like the enc28j60 one.

ecp5pll

Mario Hoffmann @hoffma_gitlab Aug 05 16:11

Hello, I wanted to have a 90 degree shifted clock. I was trying out the ecp5pll from @emard. I get it running and the clock adjustment seems to work, but somehow it does not get shifted for me. Is this currently not working with yosys and so forth, is there anything I have to take care of, or might it just be a bug on my side? Tried to search this chat a bit and just searched a bit on the internet but the things I found about it were quite old and not necessarily about my problem. Any ideas? I am using the vhdl version btw

emard @emard Aug 05 16:59

There's some order of signals and small delays between them for dynamic shifting to work. https://github.com/emard/ulx3s-misc/blob/master/examples/sdram/memtest_mister/hdl/top/top_memtest.v#L73 here is module to control phase shifts by pressing of BTN for testing of SDRAM with variable phase shift of the clock to chip

Mario Hoffmann @hoffma_gitlab Aug 05 17:01

alright, ill look at that. thanks

Mario Hoffmann @hoffma_gitlab Aug 05 17:53

Oh nice it works. My thinking was just a bit wrong and there was a little bug too. Thanks

emard @emard Aug 05 18:07

ecp5pll has possibility for fine-precision phase adjustment but this simple BTN module doesn't generate proper phaseloadreg signal https://github.com/emard/ulx3s-misc/blob/master/examples/sdram/memtest_mister/hdl/btn_ecp5pll_phase.v#L51

display

https://gitter.im/ulx3s/Lobby?at=5f3b7df7ee58011680b36cb0

emard @emard Aug 18 09:06

SSD1331 96x64 is full featured OLED beautiful contrast, but currently best buy is ST7789 1.3" 240x240 LCD less contrast but more pix and less $. Do not solder directly the display. Solder female 7-pin header and plug the display. Mechanical stabilization can be 3D printed https://github.com/emard/ulx3s/tree/master/box it will "work" properly only if whole box is printed. There is no problem with heat normally to FPGA but SSD1331 with wrong software commands can become hot to fry fingers and smoke, it happened to me once, colors faded and I just replaced display. Onboard USB-SERIAL can provide 2nd JTAG channel for openocd debugger of RISCV processor it will work but it will be VERY slow (for debug single step ok, but for transferring Mbps no).

rtc

https://gitter.im/ulx3s/Lobby?at=5f3b86a1a8c178017657caf6

emard @emard Aug 18 09:43

Yes for RTC I first saw it "works" but after few reboots I found out that it resets to compile time or something. Core could consult onboard RTC using i2c and then set unix time integer counter which will continue ticking afterwards. For setting RTC we have esp32 and other options. Btw import ntptime; ntptime.settime() will set ESP32 localtime() from a pool of network NTP servers and then esp32 can initialize onboard RTC here I have played with this https://github.com/emard/ulx3s-misc/tree/master/examples/rtc/micropython-mcp7940n/esp32

https://gitter.im/ulx3s/Lobby?at=5f3dbb34750a2741302ea427

emard @emard Aug 20 01:52

@pnru_gitlab here is 8-bit master interface. I haven't tested it very simple by reading seconds and seems ok https://github.com/emard/ulx3s-misc/blob/master/examples/rtc/i2c_master/proj/hdl/i2c_master_8bit.v

https://gitter.im/ulx3s/Lobby?at=5f3e2d1c07c30d132a9c4f58

emard @emard Aug 20 09:58

when we are at verilog, I have found on the net several i2c bidirectional bridges. Only one code worked at our board but it works only if compiled by diamond. trellis compiles but doesn't work. Can someone take a look what I have missed: bridge: https://github.com/emard/ulx3s-misc/blob/master/examples/rtc/micropython-mcp7940n/proj/hdl/i2c_bridge.v toplevel usage: https://github.com/emard/ulx3s-misc/blob/master/examples/rtc/micropython-mcp7940n/proj/top/top_i2c_bridge.v

emard @emard Aug 20 22:04

for me it works for any gpdi_scl/sda PULLMODE=UP, DOWN, or NONE so it's not pull setting. I can prepare a bitstream and micropython to ulx3s-bin example that initializes the clock setting time from NTP

emard @emard Aug 20 22:18

https://github.com/emard/ulx3s-bin/tree/master/esp32/micropython/rtc can you try this RTC esp32 example for NTP setting? >>> rtcdemo.mcp.time should advance seconds

emard @emard Aug 21 00:04

RTC traffic also appears at GPDI connector (if there's i2c chip 3.3V->5V adapter soldered on board PCA9306D). Some monitors may hold i2c lines. Also gpdi connector can be used to monitor traffic if e.g. you have hdmi breakout board
If you don't have battery, RTC will keep setting until board is powered off
If you have 2 ULX3S boards and mini-display OLED/LCD, you can connect 2 ULX3S together and on one run scopeio, which will monitor the other i2c traffic
I can prepare scope stuff for such setup because scopeio is vhdl, advanced so much that ghdl won't have chance in near future to compile it

emard @emard Aug 21 00:09

UPS but we have problem there will be 2 RTC chips colliding address :)
about i2c master 8bit. First write highest bytes 3,2,1 (order not important) and last write byte 0, this should initiate i2c transaction. byte 3=0x80 is READ, byte 3=0x00 is write
If you write 0x00 to register 0x00 (seconds) it will stop RTC. To start, it needs 0x80 written to 0x00 (MSB bit must be set) then the RTC should start "ticking"

emard @emard Aug 21 18:14

I fixed i2c_bridge.v to work with both trellis and diamond.

Paul Ruiz @pnru_gitlab Aug 21 23:35

Which way does the battery go? I think with the + side (cap) up and the - side (ribbed) to the PCB?
@emard: thanks for all the links, but your code already appears to work. The long one is interesting, it uses the same two level state machine idea that my non-working i2c controller uses.

emard @emard Aug 21 23:59

Battery goes + up (larger part of battery should be in contact with metallic holder soldered) - down (smaller part of battery in contact to big circular pad on the PCB
Glad to hear good news that my code works - it hasn't been tested on real CPU but I made some BTNs toplevel and a read and write to register 0 worked

scopeio

https://gitter.im/ulx3s/Lobby?at=5f3c27ffa05e464346d2f6ea

emard @emard Aug 18 21:11

@gkankanh MAX11125 is 1Msa/s total so e.g. if you use 4ch then each channel will be 0.25MSa/s per channel. For oscilloscope it, we have ready solution at hdl4fpga/ULX3S/scopeio you will see traces on monitor. For analysis, onboard USB-serial can do 3Mbps so it could be nearly useable. For faster ADC, yes 100 Mbit ethernet ETH8720 from ebay, module for 2.2$ and for example ebay's AN108 AD/DA module 32MSa/s input, 125MSa/s output https://www.ebay.com/itm/ADDA-Module-Data-Signal-Acquisition-High-speed-Directly-pluggable-connector-/253556250998 also scopeio supports it

how to solder headers

https://gitter.im/ulx3s/Lobby?at=5f3cd88378f4a801801336cb

emard @emard Aug 19 09:45

To have GP/GN not be swapped from "default" design, Either solder 90° FEMALE headers on top side of board (nice for PMODs directly) or straight 0° MALE pins down on bottom side of board. PMODs can also plug to other end of flat cable and pinout will be identical as if 90° was soldered onboard.

nmingen

https://gitter.im/ulx3s/Lobby?at=5f3cfbce8b8d4f633effcea7

Lawrie Griffiths @lawrie Aug 19 12:15

I am using Ubuntu 20.04, so I need to use pip3 not pip. (You can't get python2 pip on 20.04 easily).
The installation instructions for nmgen-boards says "Todo", so I installed it like the m_labs version said.
I changed the blinky example to use ULX3S_85F_Platform and ran that. It complained that tool {} was missing.
It seemed that it needed OpenFpgaLoader for upload, so I installed that, and then the blinky worked.

from nmigen import *
from nmigen_boards.ulx3s import *


class Blinky(Elaboratable):
    def elaborate(self, platform):
        led   = platform.request("led", 0)
        timer = Signal(26)

        m = Module()
        m.d.sync += timer.eq(timer + 1)
        m.d.comb += led.o.eq(timer[-1])
        return m


if __name__ == "__main__":
    platform = ULX3S_85F_Platform()
    platform.build(Blinky(), do_program=True)

https://github.com/GuzTech/ulx3s-nmigen-examples

https://github.com/greatscottgadgets/luna

SDRAM memtest

https://gitter.im/ulx3s/Lobby?at=5f4ea96249a1df0a12c0d83e

Lawrie Griffiths @lawrie Sep 01 22:04

@pnru_gitlab @Dolu1990 asked these questions about using the SDRAM, which I thought you might know something about from all your recent work on SDRAM drivers:
I'm thinking about the SDRAM
currently, the soc is at 50 mhz, and the sdram run at 100 Mhz using DDR io
but maybe we should quad pump the SDRAM, and doing some bootloader calibration to ajust read delays
i'm just currently not sure what is the critical path of the SDRAM chip themself
in other words "why they are specified to X frequancy and not more"

Dolu1990 @Dolu1990 Sep 01 22:05

Moaaaar powaaaaaaaa

emard @emard Sep 01 22:36

oooh yeea :)) if you want to push SDRAM near the edge and give it some heat, on selected designs it can push 133MHz chips to 180-200 MHz, fmax depends on each board. 12F performs better than 85F. Here's memtest https://github.com/emard/ulx3s-misc/tree/master/examples/sdram/memtest_mister shows results on DVI monitor and with BTNs can adjust phase shift dynamically and watch for errors.

Dolu1990 @Dolu1990 Sep 01 23:01

<3
Nice thanks :)
So this test controle the shift of the clock sent to the DRAM ?
(it doesn't use the programable input delay ?)

emard @emard Sep 01 23:08

Yes this has a classic sdram driver that normally needs 90° phase offset to chip hardware, but as fmax is getting higher the actual phase shift which makes it really work moves. PLL is used to provide phase shift. Paul has made a better sdram driver with cool vendor-independent delay solution with a number of NOT gates.Only ns delay per NOT gate remains vendor dependent

Dolu1990 @Dolu1990 Sep 01 23:09

ok :D

Paul Ruiz @pnru_gitlab 00:02

@lawrie @Dolu1990 I am not sure I understand the SDRAM questions. In any case, my latest version is here: https://gitlab.com/pnru/cortex/-/blob/master/sdram.v
In particular note new lines 45-47 - I am not sure why, but this mod generally pushes Fmax up to about 200MHz (it depends a bit on the NextPNR seed).

I am not sure what you mean by "using DDR io" - does the SDRAM chip on the ULX3S support DDR? Maybe you mean by DDR that it runs at twice the speed of the CPU or that it uses burst size 2?

I don't know what the critical path in the SDRAM chip is, but I do have a hypothesis. When working with a CAS delay of 3 clocks, the data really arrives after 2 clocks plus 6-7ns (spending on the speed grade). If you clock a grade 6 chip (PC166) faster, a clock cycle will take less than 6ns and the data will only arrive after the third rising clock edge. My guess is that the 6-7ns is related to the speed of the sense amplifiers or something like that.

resource utilization

https://gitter.im/ulx3s/Lobby?at=5f4f8c30d4f0f55ebbf93007

Dolu1990 @Dolu1990 Sep 02 14:12

Is somebody aware of a way to get hearchical ressource utilisation report out from yosys/next-pnr for ECP5 ?
Basicaly, trying to nail down the ressource usage

David Shah @daveshah1 Sep 02 14:18

You can get a hierarchical report with Yosys by passing -noflatten to synth_ecp5

ps2 keyboard

https://gitter.im/ulx3s/Lobby?at=5f57e59c59ac794e02f71d14

Kid CUDA @KidCUDA_gitlab Sep 08 22:12

anyone used a PS2 keyboard with ULX3S?
like a proper PS2 keyboard with the pins adapted to USB?
is a level shifter needed or is the USB port 5V-data-tolerant?
from the schematic it doesn't look 5V tolerant but I'm not sure how else it would work with just a pure PS2 adapter as suggested in the docs

emard @emard Sep 08 22:52

@KidCUDA_gitlab US2 pins are 5V tolerant, limited by R and Zener diodes. Still some PS/2 keyboards don't accept 3.3V levels. Best is to obtain combo PS/2+USB they usually work in both modes for ULX3S
PS/2 is normally used over OTG connector for most of our retro-computing cores, apple1-2, ti99, zx, vic20, QL just to name a few

cortex

source: https://gitlab.com/pnru/cortex

https://gitter.im/ulx3s/Lobby?at=5f500a7eec534f584fdbeb15

Paul Ruiz @pnru_gitlab Sep 02 23:11

    8s is super-comfortable! Btw I wonder how did cortex start, before it ever booted they need some filesystem to hold files. Is cortex filesystem mountable by modern linux? How did they made it in early times?

The Cortex was a traditional home computer with Basic in its day. Running Unix on it was my project some 6-7 years ago. It was a long journey: porting a C compiler and tool chain, building simple kernels with a linked in user program (downloaded to the H/W via something similar to S-records), etc. When the time for disk access came, I used a tool to create & manage disk images.

For the original Unix, the file system was almost the first thing that was built, after the assembler (that is how a.out got its name: assembler output). An empty disk image was written by a custom format program. Files were then loaded from paper tape. Some 1969/1970 Unix code can be found here:
https://www.tuhs.org/cgi-bin/utree.pl
In its first incarnations it was all assembler, but many of the core ideas were already there. Some more background is here:
https://www.bell-labs.com/usr/dmr/www/hist.html

emard @emard Sep 02 23:14

Ahaaaa so unix was not all the time available on cortex hardware. Still I'd wanted to know how did you initially start with populated filesystem. Normally e.g. if we have linux on riscv, we can mount the same partition on x86 PC, copy files and and it will work on riscv, but how was this done on cortex?

So If I understood, you have a tool that from a directory creates disk image, but there's currently no support to actually mount cortex fs on linux for example. linux has some possibility to write a user-space fs driver like "fuse" but I ghess thats difficult and fragile

Paul Ruiz @pnru_gitlab Sep 02 23:29

You can follow my journey here, in 315 commits:
https://www.jslite.net/cgi-bin/9995/timeline?n=400&y=all&v=0

I use a program ("ufs") which creates a disk image from scratch and then adds files to it. The source code is here:
https://www.jslite.net/cgi-bin/9995/dir?ci=84b2a75947eb76db&name=fsutil

Even on the mini Cortex hardware, the CF Card uses FAT formatting and has an image file on it. I make sure the image is contiguous and the boot loader lets the Unix disk driver know in which sector the image starts. This way I can simply copy disk images to the CF card without needing to use special tools.

Actually, the card also has disk images for other OS's as well - MDEX and NOS, which are somewhat similar to CP/M and MS-DOS 3 respectively.

emard @emard Sep 02 23:44

There has been a lot of concentrated effort! The idea to use contiguous file in FAT is very good, so the CF itself can be easily written from laptop.

Paul Ruiz @pnru_gitlab Sep 02 23:53

Thank you. The ulx3s Cortex has it even easier: because of the ESP32, now I don't even have to worry about things being contiguous and I can ftp disk images without having to handle the SD card.

emard @emard Sep 03 00:34

yeees it was a piece of luck that for esp32 appeared good micropython support with almost all important things working and that spi-jtag adventure turned out successful. I have ulx3s with SD in a box and once inserted SD I never move out, just ftp files. Things will be even better when WROVER-E prototype starts working, 4MB RAM, 16MB FLASH no more out of memory. Bitstreams could be unzipped on-the-fly, even larger FLASH chips supported with 64K and 256K erase blocks (esp32 must buffer data size of erase block and now we are struggling with 4K buffers)

saxonsoc audio

https://gitter.im/ulx3s/Lobby?at=5f6482c3603d0b37f43d3ec0

Lawrie Griffiths @lawrie Sep 18 11:49

I have a 4-cpu 85F SaxonSoc version with music, working now.

It is now inSmp/bitstreams/ulx3s_85f_blue_4core_saxonsoc.bit
I renamed images as oldimages and the new one are in Smp/images.
You need dtb, uImage and you need to untar the new rootfs.tar.
You will also need:

root@buildroot:~# cat .asoundrc
pcm.!default {
    type            plug
    slave.pcm       "softvol"   #make use of softvol
}

pcm.softvol {
    type         softvol
    slave {
        pcm         "hw:0,0"      #redirect the output to dmix (instead of "hw:0,0")
    }
    control {
           name        "PCM"       #override the PCM slider to set the softvol volume level globally
        card     0
    }
}

To play music do: mpg123 -T -f 4096 -m file.mp3.
Or to play in the background nohup mpg123 -T -f 4096 -m file.mp3 &
It is set up for a 64MB blue 85f.

https://gitter.im/ulx3s/Lobby?at=5f648d8cf51808513b4f7db5

olu1990 @Dolu1990 Sep 18 12:35

.asoundrc isn't necessary, it just add volume controles in alsamixer app
I would suggest to not add the .asoundrc for single core versions, as it add quite a bit of overhead
the -m of mpg123 is for mono, if the mp3 bit rate isn't to high, it might be fine in stereo
(for single core)

saxonsoc rtc

https://gitter.im/ulx3s/Lobby?at=5f69eb5d6a6e094525ac61f5

https://gitter.im/ulx3s/Lobby?at=5f69f087e1dd7c19548aad12

Dolu1990 @Dolu1990 Sep 22 14:39

got the rtc to start counting seconds and read it via :

i2cset -y 0 0x6F 0x00 0x80
sleep 4
i2cget -y 0 0x6F 0x00

https://gitter.im/ulx3s/Lobby?at=5f6a4562e1dd7c19548b96f0

Lawrie Griffiths @lawrie Sep 22 20:41

oot@buildroot:~# cat date.sh 
R6=`i2cget -y 0 0x6f 0x06`
R5=`i2cget -y 0 0x6f 0x05`
R4=`i2cget -y 0 0x6f 0x04`
R2=`i2cget -y 0 0x6f 0x02`
R1=`i2cget -y 0 0x6f 0x01`

YY="${R6:2:2}"
MON="$((${R5:2:2}-20))"
DD="${R4:2:2}"
HH="${R2:2:2}"
MM="${R1:2:2}"

echo "20$YY-$MON-$DD $HH:$MM"
root@buildroot:~# ./date.sh 
2020-9-22 19:40

date -s "`./date.sh`"

https://gitter.im/ulx3s/Lobby?at=5f6a69588fe6f11963554984

emard @emard Sep 22 23:15

#include <stdio.h>
#include <stdlib.h>

#define I2C_SLAVE 0x703
#define O_RDWR 2

int i2c_rtc;

void rtc_open(int addr)
{
  i2c_rtc = open("/dev/i2c-0", O_RDWR);
  ioctl(i2c_rtc, I2C_SLAVE, addr);
}

void rtc_read(unsigned char *buf, int reg, int n)
{
  buf[0] = reg;
  write(i2c_rtc, buf, 1);
  read(i2c_rtc, buf, n);
}

void i2cdemo(void)
{
  int i;
  unsigned char buf[7];
  // mask for BCD          SEC   MIN   HOUR  WKDAY DAY   MONTH YEAR
  unsigned char mask[7] = {0x7F, 0x7F, 0x3F, 0x07, 0x3F, 0x1F, 0xFF};

  rtc_read(buf, 0, sizeof(buf));
  for(i = sizeof(buf)-1; i >= 0; i--)
    printf(" %02x", buf[i] & mask[i]);
  printf("\n");
}

int main(int argc, char *argv[])
{
  int i;
  rtc_open(0x6F);
  for(i = 0; i < 60; i++)
  {
    i2cdemo();
    sleep(1);
  }
  return 0;
}
root@buildroot:/home/root/rtc# ./a.out 
 20 09 22 02 21 14 27
 20 09 22 02 21 14 28
 20 09 22 02 21 14 29
 20 09 22 02 21 14 30
 20 09 22 02 21 14 31

saxonsoc jtag

https://gitter.im/ulx3s/Lobby?at=5f78c209dfe47e4d57464c10

Lawrie Griffiths @lawrie Oct 03 20:25

The pins to connect to are these - https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.1/hardware/synthesis/radiona/ulx3s/smp/ulx3s_v20_linux_uboot.lpf#L342-L348

emard @emard Oct 03 20:26

I tried to upload SVF file and it works, (fast). Yes, this pins connection is important. Is there a simple JTAG openocd scan command I can test it to make sure I connected all
Some command similar to

jtag newtap lfe5 tap -expected-id 0x21111043 -irlen 8 -irmask 0xFF -ircapture 0x5

Dolu1990 @Dolu1990 Oct 03 20:29

hoo when openocd run it scan everything

emard @emard Oct 03 20:29

yes yes I see it on above linked script

Dolu1990 @Dolu1990 Oct 03 20:30

i'm not sur there a command to rescan, just rerun it ^^

emard @emard Oct 03 20:31

OK I need to make a bit on the solder and pins to board, then I will test it and when I get vexrisc scanned by openocd jtag I will put it online for remote access

Dolu1990 @Dolu1990 Oct 03 20:31

you should get a scan like 0x10001FFF

Lawrie Griffiths @lawrie Oct 03 20:33

@Dolu1990 Doesn't @emard need to build your version of openocd - https://github.com/SpinalHDL/openocd_riscv

Dolu1990 @Dolu1990 Oct 03 20:34

Yes
so :
You can source the source.sh, and then do a saxon_clone; saxon_openocd
this will build it
Then modify https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.1/bsp/radiona/ulx3s/smp/openocd/usb_connect.cfg#L2 to match the jtag you have installed, and then saxon_openocd_connect

Dolu1990 @Dolu1990 Oct 03 21:02

sudo apt-get install libtool automake libusb-1.0.0-dev texinfo libusb-dev libyaml-dev pkg-config for the full depedency on debian

emard @emard 00:00

Escape character is '^]'.
Open On-Chip Debugger
> init 
> scan_chain
   TapName             Enabled  IdCode     Expected   IrLen IrCap IrMask
-- ------------------- -------- ---------- ---------- ----- ----- ------
 0 fpga_spinal.bridge     Y     0x10001fff 0x10001fff     4 0x01  0x0f

Got openocd to connect

https://gitter.im/ulx3s/Lobby?at=5f7c33646e0eb844696af0a2

Lawrie Griffiths @lawrie 11:05

You then need a usb JTAG device, preferably an FT2232 one, and you connect the pins to gn0 - gn3. I have not used openocd with SaxonSoc for a while, but @Dolu1990 uses it all the time.

micropython socks

https://gitter.im/ulx3s/Lobby/archives/2020/10/10?at=5f820bfb07361f0cc6430489

kost @kost Oct 10 19:31 UTC

since you guys around SaxonSoc made such a great progress. I had to do my part of the promise.
Just released socks server for micropython at https://github.com/kost/micropython-socks
that means you can tunnel any SOCKS5 connection over ESP32
since micropython does not come with NAT support, that means you can go to the internet over ESP32 using SOCKS server.
Installation is simple if you have connected ESP32 already to the internet:
You have to run this on ulx3s repl shell:

import upip
upip.install('micropython-socks')

and then you can just simply say:

import socks
socks.start()

it will start listening on 0.0.0.0:1080 for SOCKS5 connections.
Then you can simply from SaxonSoc test it with the following (or any other host):

curl --socks5 192.168.4.1:1080 http://ifconfig.co
permalink
Colorlight 5A-75B


Board version: v7.0

  • Lattice ECP5 LFE5U-25F-6BG256C (product page)
  • Winbond 25Q32JVSIQ, 32 Mbits SPI flash (datasheet)
  • 2x Broadcom B50612D Gigabit Ethernet PHYs (datasheet)
  • 2x ESMT M12L16161A-5T 1M x 16bit 200MHz SDRAMs (organized as 1M x 32bit) (datasheet)
  • 12x 74HC245T Octal Bidirectional Transceiver (used for level translation to 5V)
cl-5a-75b-v70-front-800.jpg

links

chubby75

original protocol

replace level shifters to get input

https://twitter.com/Claude1079/status/1231194849350647808

 SN74CBT3245APW 8bit bidirectional FET switches
QS3245QG

colorLight5A-75b.jpg

chiselwatt

https://github.com/antonblanchard/chiselwatt/commit/5a7fcbc8142ed2b390e1f8bfaaa801fe09a60351

UART RX is on J19, labelled key+ on the silk screen on the back
UART TX is on J1, pin 1.

LOCATE COMP "clock" SITE "P6";

LOCATE COMP "io_tx" SITE "F3";
LOCATE COMP "io_rx" SITE "M13";

litex

basic example of litex on colorLight 5A-75B based on fpga_101/lab004

fpga pin mapping

https://twitter.com/adamgreig/status/1297255957320421383

I don't want to load a new image onto this totally blind, so I used the prjtrellis tools (https://github.com/YosysHQ/prjtrellis/) to write a script (https://github.com/adamgreig/cl/blob/master/pins.py) which works out input/output/bidi for all pins used in any ECP5 bitstream. It found only one unused pin...

https://github.com/adamgreig/cl/blob/master/pins.py

fpga images

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M8S PRO

Board sticker: M8S PRO R4 S912 3G 32G DDR4 DQ



M8S-PRO.jpg

It doesn't have button soldered, it works like power button in android

Serial port is marked on bottom of board (tx/rx are from cpu perspective)

probably: https://www.geekbuying.com/item/MECOOL-M8S-PRO-S912-KODI-17-0-4K-HDR10-3GB-DDR4-32GB-eMMC-TV-Box-380737.html

Android info

Android 7.1 bootlog from serial: m8s-android-bootlog.txt.gz

U-Boot 2015.01-g9331ff1-dirty (Mar 15 2018 - 16:16:24)

DRAM:  3 GiB
...
        aml_dt soc: gxm platform: q20xrmii variant: 3g
        dtb 0 soc: gxm   plat: q20xrmii   vari: 2g
        dtb 1 soc: gxm   plat: q20xrmii   vari: 3g
      Find match dtb: 1
...
parts: 10
00:      logo	0000000002000000 1
01:  recovery	0000000002000000 1
02:       rsv	0000000000800000 1
03:       tee	0000000000800000 1
04:     crypt	0000000002000000 1
05:      misc	0000000002000000 1
06:      boot	0000000002000000 1
07:    system	0000000080000000 1
08:     cache	0000000020000000 2
09:      data	ffffffffffffffff 4

M8SPRO:/ # uname -a
Linux localhost 3.14.29 #46 SMP PREEMPT Thu Apr 12 19:43:12 CST 2018 armv8l

M8SPRO:/ # cat /proc/cmdline
rootfstype=ramfs init=/init console=ttyS0,115200 no_console_suspend earlyprintk=aml-uart,0xc81004c0 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 androidboot.selinux=permissive logo=osd1,loaded,0x3d800000,1080p60hz maxcpus=8 vout=1080p60hz,enable hdmimode=1080p60hz cvbsmode=576cvbs hdmitx= cvbsdrv=0 pq= androidboot.firstboot=0 jtag=apao androidboot.hardware=amlogic mac=D0:76:58:0E:63:A3 androidboot.mac=D0:76:58:0E:63:A3 androidboot.slot_suffix=_a buildvariant=userdebug

M8SPRO:/ # cat /proc/cpuinfo
Processor	: AArch64 Processor rev 4 (aarch64)
processor	: 0
processor	: 1
processor	: 2
processor	: 3
processor	: 4
processor	: 5
processor	: 6
processor	: 7
Features	: fp asimd evtstrm aes pmull sha1 sha2 crc32 wp half thumb fastmult vfp edsp neon vfpv3 tlsi vfpv4 idiva idivt 
CPU implementer	: 0x41
CPU architecture: 8
CPU variant	: 0x0
CPU part	: 0xd03
CPU revision	: 4

Hardware	: Amlogic
Serial		: 220a82006da41365fedf301742726826

M8SPRO:/ # free
		total        used        free      shared     buffers
Mem:       2876604416  2210639872   665964544           0    31326208
-/+ buffers/cache:     2179313664   697290752
Swap:       524283904           0   524283904

M8SPRO:/ # df
ilesystem        1K-blocks    Used Available Use% Mounted on
mpfs               1404592     504   1404088   1% /dev
tmpfs               1404592       0   1404592   0% /mnt
/dev/block/system   2031440  973788   1057652  48% /system
/dev/block/data    26969964 3050864  23919100  12% /data
/dev/block/cache     507848    2860    504988   1% /cache
/dev/block/tee         5115      45      5070   1% /tee
/dev/fuse          26969964 3050864  23919100  12% /mnt/runtime/default/emulated
/dev/fuse          26969964 3050864  23919100  12% /mnt/runtime/read/emulated
/dev/fuse          26969964 3050864  23919100  12% /mnt/runtime/write/emulated


recovery sd

https://www.cnx-software.com/2016/11/19/how-to-create-a-bootable-recovery-sd-card-for-amlogic-tv-boxes/

amlogic info

http://www.linux-meson.com/doku.php

armbian

https://forum.armbian.com/topic/12162-single-armbian-image-for-rk-aml-aw-aarch64-armv8/

dpavlin@nuc:~/Downloads$ xzcat Armbian_20.09_Arm-64_bullseye_current_5.8.5.img.xz | dd iflag=fullblock oflag=direct conv=fsync status=progress bs=1M of=/dev/sdb
dpavlin@nuc:~/Downloads$ sudo mount /dev/sdb1 /mnt/sdb1/
dpavlin@nuc:~/Downloads$ cd /mnt/sdb1/

root@nuc:/mnt/sdb1# cp u-boot-s905x-s912 u-boot.ext

root@nuc:/mnt/sdb1# vi extlinux/extlinux.conf

root@nuc:/mnt/sdb1# grep -v '^#' extlinux/extlinux.conf
LABEL Armbian
LINUX /zImage
INITRD /uInitrd

FDT /dtb/amlogic/meson-gxm-q201.dtb
APPEND root=LABEL=ROOTFS rootflags=data=writeback rw console=ttyAML0,115200n8 console=tty0 no_console_suspend consoleblank=0 fsck.fix=yes fsck.repair=yes net.ifnames=0


Note that this board uses meson-gxm-q201.dtb which is internal rmii to make ethernet work!

issue reboot update from android shell to boot from sdcard

ath10k wifi sdio firmware

After booting, you will get error message about missing firmware:

[    7.861827] ath10k_sdio mmc2:0001:1: Failed to find firmware-N.bin (N between 2 and 6) from ath10k/QCA9377/hw1.0: -2
[    7.861838] ath10k_sdio mmc2:0001:1: could not fetch firmware files (-2)

Package firmware-atheros is installed, so it's a bit puzzeling what file is missing, however, if we go to

https://github.com/kvalo/ath10k-firmware.git

we can find sdio firmware at https://github.com/kvalo/ath10k-firmware/tree/master/QCA9377/hw1.0/untested

dpavlin@m8s:~/ath10k-firmware$ git remote -v
origin	https://github.com/kvalo/ath10k-firmware.git (fetch)
origin	https://github.com/kvalo/ath10k-firmware.git (push)

dpavlin@m8s:~/ath10k-firmware$ sudo cp QCA9377/hw1.0/untested/firmware-sdio-5.bin_WLAN.TF.1.1.1-00061-QCATFSWPZ-1 /lib/firmware/ath10k/QCA9377/hw1.0/firmware-sdio-5.bin

After running nmtui and configuring wifi it's available but dies after a while under load.

kernel source

https://github.com/150balbes/Amlogic_s905-kernel

u-boot source

https://github.com/150balbes/Amlogic_S905-u-boot

gpiod

sudo apt install gpiod

button - gpio 2

root@arm-64:~# gpioget gpiochip0 2 # not pressed
1
root@arm-64:~# gpioget gpiochip0 2 # pressed
0

led - gpio 9

root@arm-64:~# gpioset gpiochip0 9=0 # red

root@arm-64:~# gpioset gpiochip0 9=1 # blue (default)

u-boot

old https://github.com/endlessm/u-boot-meson

I wanted serial console which seems to be missing from armbian build above

wiki seems to suggest repository

https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic

but we are going to use upstream u-boot

dpavlin@m8s:~/u-boot-amlogic$ git remote -v
github	https://github.com/u-boot/u-boot (fetch)

dpavlin@m8s:~/u-boot-amlogic$ libretech-cc_defconfig
dpavlin@m8s:~/u-boot-amlogic$ make -j 8
dpavlin@m8s:~/u-boot-amlogic$ cp u-boot.bin /boot/

abort u-boot with key press and boot new one with

fatload mmc 1 0x1000000 u-boot.bin
go 0x1000000
permalink
OrangeCrab

https://gregdavill.github.io/OrangeCrab/

https://github.com/gregdavill/OrangeCrab

[Mon Sep 14 13:46:12 2020] usb 2-2.3: new full-speed USB device number 8 using xhci_hcd
[Mon Sep 14 13:46:12 2020] usb 2-2.3: New USB device found, idVendor=1209, idProduct=5af0, bcdDevice= 1.01
[Mon Sep 14 13:46:12 2020] usb 2-2.3: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[Mon Sep 14 13:46:12 2020] usb 2-2.3: Product: OrangeCrab r0.2 DFU Bootloader v3.1
[Mon Sep 14 13:46:12 2020] usb 2-2.3: Manufacturer: GsD

permalink
ULX3S
Contents: [Dobrica Pavlinušić's random unstructured stuff]


first steps

Here I will try to document correct order to read documentation to get setup for ULX3S:

https://github.com/emard/ulx3s-bin/blob/master/README.md

There is also useful things from chat at ULX3S Lobby

udev rule

ujprog

git clone https://github.com/f32c/tools f32c-tools
cd f32c-tools/ujprog/
dpavlin@x200:/mnt/nuc/FPGA/f32c-tools/ujprog$ rm ujprog
dpavlin@x200:/mnt/nuc/FPGA/f32c-tools/ujprog$ make -f Makefile.linux
cc -Wall -D__linux__ -std=gnu99 -static ujprog.c /usr/lib/x86_64-linux-gnu/libftdi.a /usr/lib/x86_64-linux-gnu/libusb.a -o ujprog
dpavlin@x200:/mnt/nuc/FPGA/f32c-tools/ujprog$ sudo cp ujprog /usr/local/bin/

  • create udev rule

passthru to access esp32

source at https://github.com/emard/ulx3s-passthru

dpavlin@x200:/mnt/nuc/FPGA/ulx3s-bin/fpga/passthru/passthru-v20-85f$ ujprog -j flash ulx3s_85f_passthru.bit
ULX2S / ULX3S JTAG programmer v 3.0.92 (built Nov 19 2019 10:55:50)
Using USB cable: ULX3S FPGA 12K v3.0.3
[Wed Nov 20 18:02:01 2019] ftdi_sio ttyUSB0: FTDI USB Serial Device converter now disconnected from ttyUSB0
[Wed Nov 20 18:02:01 2019] ftdi_sio 1-5.2:1.0: device disconnected
Programming: 100%
Completed in 24.36 seconds.
[Wed Nov 20 18:02:25 2019] usb 1-5.2: reset full-speed USB device number 56 using ehci-pci
[Wed Nov 20 18:02:26 2019] ftdi_sio 1-5.2:1.0: FTDI USB Serial Device converter detected
[Wed Nov 20 18:02:26 2019] usb 1-5.2: Detected FT-X
[Wed Nov 20 18:02:26 2019] usb 1-5.2: FTDI USB Serial Device converter now attached to ttyUSB0


update size of your FPGA

dpavlin@x200:/mnt/nuc/FPGA/ulx3s-bin$ usb-jtag/linux-amd64/ftx_prog --product "ULX3S FPGA 85K v3.0.3"

power cycle board to get new usb id, test that it's supported by ujprog

dpavlin@x200:/mnt/nuc/FPGA/ulx3s-bin$ ujprog -r

esptool and esp32 booting problems

You should be using ecptool from ulx3s-bin repository to quite @emard from https://gitter.im/ulx3s/Lobby#dark-theme

OK then. If you have issues with ESP32 not booting with SD card but booting without SD card then then the fuse burn script from ulx3s-bin should be run. So far so good, you erased its flash, try linux. If no issue then can try to flash micropython and my new ESP32 OTA programmer ecp5.py end uftpd.py

I have wisely taken some esptool.py which works and frozen it in ulx3s, versions change all the time and maybe you took something in the middle of development action :)

install micropython

https://github.com/emard/esp32ecp5/

dpavlin@nuc:/nuc/FPGA$ git clone https://github.com/emard/esp32ecp5/
dpavlin@nuc:/nuc/FPGA$ cd esp32ecp5/
dpavlin@x200:/mnt/nuc/FPGA/esp32ecp5$ wget https://micropython.org/resources/firmware/esp32-idf3-20191120-v1.11-580-g973f68780.bin


It's important to erase flash or micropyhton will complain about corrupt fat filesystem like:

FAT filesystem appears to be corrupted. If you had important data there, you
may want to make a flash snapshot to try to recover it. Otherwise, perform
factory reprogramming of MicroPython firmware (completely erase flash, followed
by firmware programming).

dpavlin@x200:/mnt/nuc/FPGA/esp32ecp5$ ../ulx3s-bin/esp32/serial-uploader/esptool.py --chip esp32 --port /dev/ttyUSB0 erase_flash
esptool.py v2.6-beta1
Serial port /dev/ttyUSB0
Connecting....
Chip is ESP32D0WDQ6 (revision 1)
Features: WiFi, BT, Dual Core, 240MHz, VRef calibration in efuse, Coding Scheme None
MAC: a4:cf:12:55:c5:60
Uploading stub...
Running stub...
Stub running...
Erasing flash (this may take a while)...
Chip erase completed successfully in 8.7s
Hard resetting via RTS pin...


dpavlin@x200:/mnt/nuc/FPGA/esp32ecp5$ ../ulx3s-bin/esp32/serial-uploader/esptool.py --chip esp32 --port /dev/ttyUSB0 --baud 460800 write_flash -z 0x1000 esp32-idf3-20191120-v1.11-580-g973f68780.bin
esptool.py v2.6-beta1
Serial port /dev/ttyUSB0
Connecting....
Chip is ESP32D0WDQ6 (revision 1)
Features: WiFi, BT, Dual Core, 240MHz, VRef calibration in efuse, Coding Scheme None
MAC: a4:cf:12:55:c5:60
Uploading stub...
Running stub...
Stub running...
Changing baud rate to 460800
Changed.
Configuring flash size...
Auto-detected Flash size: 4MB
Compressed 1240192 bytes to 783187...
Wrote 1240192 bytes (783187 compressed) at 0x00001000 in 18.7 seconds (effective 529.3 kbit/s)...
Hash of data verified.

Leaving...
Hard resetting via RTS pin...

dpavlin@x200:/mnt/nuc/FPGA/esp32ecp5$ microcom -p /dev/ttyUSB0
connected to /dev/ttyUSB0
Escape character: Ctrl-\
Type the escape character to get to the prompt.

>>>
> help()
Welcome to MicroPython on the ESP32!

For generic online docs please visit http://docs.micropython.org/

For access to the hardware use the 'machine' module:

import machine
pin12 = machine.Pin(12, machine.Pin.OUT)
pin12.value(1)
pin13 = machine.Pin(13, machine.Pin.IN, machine.Pin.PULL_UP)
print(pin13.value())
i2c = machine.I2C(scl=machine.Pin(21), sda=machine.Pin(22))
i2c.scan()
i2c.writeto(addr, b'1234')
i2c.readfrom(addr, 4)

Basic WiFi configuration:

import network
sta_if = network.WLAN(network.STA_IF); sta_if.active(True)
sta_if.scan()                             # Scan for available access points
sta_if.connect("<AP_name>", "<password>") # Connect to an AP
sta_if.isconnected()                      # Check for successful connection

Control commands:
  CTRL-A        -- on a blank line, enter raw REPL mode
  CTRL-B        -- on a blank line, enter normal REPL mode
  CTRL-C        -- interrupt a running program
  CTRL-D        -- on a blank line, do a soft reset of the board
  CTRL-E        -- on a blank line, enter paste mode

For further help on a specific object, type help(obj)
For a list of available modules, type help('modules')

webrepl

dpavlin@klin:/klin/FPGA$ git clone https://github.com/hyperglitch/webrepl



You can send files from command-line:

dpavlin@x200:/mnt/nuc/FPGA/webrepl$ ./webrepl_cli.py -p ulx3s ../esp32ecp5/ecp5.py 192.168.3.130:/
op:put, host:192.168.3.130, port:8266, passwd:ulx3s.
../esp32ecp5/ecp5.py -> /ecp5.py
Remote WebREPL version: (1, 11, 0)
Sent 22777 of 22777 bytes
dpavlin@x200:/mnt/nuc/FPGA/webrepl$ ./webrepl_cli.py -p ulx3s ../esp32ecp5/uftpd.py 192.168.3.130:/
op:put, host:192.168.3.130, port:8266, passwd:ulx3s.
../esp32ecp5/uftpd.py -> /uftpd.py
Remote WebREPL version: (1, 11, 0)
Sent 19482 of 19482 bytes


open source toolchain

Just use kost's binary builds: https://github.com/alpin3/ulx3s/releases

Or nightly builds: https://github.com/open-tool-forge/fpga-toolchain/releases

this is old and needs update

dpavlin@klin:/klin/FPGA$ git clone https://github.com/SymbiFlow/prjtrellis
dpavlin@klin:/klin/FPGA/prjtrellis$ ./download-latest-db.sh 

dpavlin@klin:/klin/FPGA/prjtrellis$ cd libtrellis/
dpavlin@klin:/klin/FPGA/prjtrellis/libtrellis$ sudo apt-get install libpython3-dev libboost-python-dev libboost-filesystem-dev libboost-thread-dev libboost-program-options-dev
dpavlin@klin:/klin/FPGA/prjtrellis/libtrellis$ cmake -DCMAKE_INSTALL_PREFIX=/usr/local .
dpavlin@klin:/klin/FPGA/prjtrellis/libtrellis$ make
sudo make install


dpavlin@klin:/klin/FPGA/nextpnr$ cmake -DARCH=ecp5 -DBUILD_GUI=OFF -DTRELLIS_ROOT=../prjtrellis/ .
make
make install





diamond

https://github.com/jandob/lattice-diamond-archlinux/blob/master/eth0DummyToggle

docker

https://gitter.im/ulx3s/Lobby?at=5dff4b08d2dadb38935c570a

https://github.com/dok3r/diamond/

docker run -it -v /host/fpga:/fpga -- local /host/fpga will end up in /fpga in docker

yes path will be fine
you will be missing make
so inside container you need to yum install make
and yum install libxslt
export ETHMAC=b0:5a:da:XX:XX:XX
set your MAC
docker run -it -v /media/internal/FPGA:/fpga -e LM_LICENSE_FILE=/fpga/license.dat --mac-address=$ETHMAC --privileged --ipc host -v /dev/bus/usb/:/dev/bus/usb/ dok3r/diamond:latest
run docker
yum install make libxslt
go tu project inside fpga folder and find makefile for diamond and then just make

then you share it with docker container with -v /yourHOSTfpgadir:/fpgadockerdir -e LM_LICENSE_FILE=/fpgadockerdir
for version you need to use like this dok3r/diamond:version
versions are here
https://hub.docker.com/r/dok3r/diamond/tags
docker run -it -v /media/internal/FPGA:/fpga -e LM_LICENSE_FILE=/fpga/license.dat --mac-address=$ETHMAC --privileged --ipc host -v /dev/bus/usb/:/dev/bus/usb/ dok3r/diamond:v3.7
like this
Not understanding -v /media/internal/FPGA
that is my local FPGA folder with samples and license.dat
it will mount on docker /fpga
and I see now that I need to share prjtrallis folder to docker so it can do ecppll
docker run -it -v /media/internal/FPGA:/fpga -v /local/prjtrellis/libtrellis:/mt/scratch/tmp/openfpga/prjtrellis/libtrellis -e LM_LICENSE_FILE=/fpga/license.dat --mac-address=$ETHMAC --privileged --ipc host -v /dev/bus/usb/:/dev/bus/usb/ dok3r/diamond:v3.7
but for that we will need @kost
we probably need ecppll and tools already there and compiled with centos- maybe just binaries

NES

https://gitter.im/ulx3s/Lobby?at=5de033f49319bb5190a9c3b6

oberon

https://gitter.im/ulx3s/Lobby?at=5e007d1e8897197969e3331c

So, I have now managed to build oberon with diamond 3.7.
What I have to do is:

1. Build it with diamond 3.11, which fails
2. mv clocks clocks_save
3. make clean
4. cp -r clocks_save clocks
5. run docker for diamond 3.7
6. edit synpbase/bin/config/platform_check to allow 5.* linux.
7. make
8. Use ujprog in host linux to upload generated bit file

Thanks @kost for adding for adding make and libxslt to the docker image. It would be useful if you could patch the platform_check to allow versions before 3.11 to run on 5.* linux.
I got a lot of errors in the diamond 3.7 docker build, but the .bit file was created.
I can now run oberon and can see windows on the screen, but I don't have a working mouse or keyboard. I would need Goran's USB board to get both mouse and keyboard.
@lawrie i fixed in latest v3.7 - just make sure that you're running latest:

docker pull dok3r/diamond:v3.7

woohoo! Cool
@kost I pulled the latest v3.7 about 10 minutes ago, but still had to edit platform_check.
synpbase/bin/config/platform_check has:

        case $VERSION in
            4.* | 3.* | 2.4.* | 2.6.* )

It needs:

        case $VERSION in
            5.* | 4.* | 3.* | 2.4.* | 2.6.* )

I did the docker pull to make sure I had the latest version.
I changed oberon makefile to generate clocks in already existing directory to get rid of annoying mkdir clocks
In my instructions above it is safer to do make ECPPLL=echo in docker, so that it does not try to use ecppll, but uses the saved clocks that were generated on host linux.

21f repack from 25f image

ecpunpack --input ulx3s_25.bit --textcfg ulx3s_12f.config --idcode 0x41111043
ecppack --input ulx3s_12f.config --bit ulxs3_12f.bit --idcode 0x21111043


compress bitstream

ecppack --compress

esp32ps2

https://github.com/emard/esp32ps2

saxonsoc

linux

Instructions at https://github.com/lawrie/saxonsoc-ulx3s-bin/tree/master/linux
work for me on 85f :-)

https://gitter.im/ulx3s/Lobby?at=5de8ba2f08d0c961b7f3a25f

git clone https://github.com/SpinalHDL/buildroot.git -b saxon buildroot
git clone https://github.com/SpinalHDL/linux.git -b vexriscv --depth 1 linux
cd buildroot
cp board/spinal/saxon_default/linux_nonet.config board/spinal/saxon_default/linux.config
# Add extra options to board/spinal/saxon_default/linux.config
make spinal_saxon_default_defconfig
make linux-rebuild all -j$(nproc)
output/host/bin/riscv32-linux-objcopy -O binary output/images/vmlinux output/images/Image
# Make sure Image is at least 116KB less than 4MB

85f version

https://gitter.im/ulx3s/Lobby?at=5dea74995ac7f22fb57055ae

https://github.com/lawrie/saxonsoc-ulx3s-bin/blob/master/linux/README.md

https://github.com/lawrie/saxonsoc-ulx3s-bin/tree/master/linux/u-boot

https://github.com/SpinalHDL/SaxonSoc/tree/dev/bsp/Ulx3sLinuxUboot

leds

https://gitter.im/ulx3s/Lobby?at=5dec101f46397c721ca4c814

#!/bin/sh
cd /sys/class/gpio
echo 488 > export
echo out > gpio488/direction
for i in 1 0 1 0 1 0
do
  sleep  0.1
  echo   $i > gpio488/value
done


slirp

https://gitter.im/ulx3s/Lobby?at=5df1467d0616d6515e20d197

modifications

https://gitter.im/ulx3s/Lobby?at=5dfced993e3f133894ca9b4b

u-boot config for 85f with 64M SDRAM

Modify bootcmd to include:

load mmc 0:1 0x80000000 /boot/uImage
load mmc 0:1 0x81EF0000 /boot/dtb
fdt add 0x81EF0000
fdt memory 0x80000000 0x04000000
bootm 0x80000000 - 0x81EF0000

ppp networking

smp support

https://gitter.im/ulx3s/Lobby?at=5f4ea80bd4f0f55ebbf6ec33

https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.1/bsp/radiona/ulx3s/smp

Instructions there need a bit of modification to run on blue 85f board with 64Mb of ram:

# Sourcing the build script
source SaxonSoc/bsp/radiona/ulx3s/smp/source.sh

# Clone opensbi, u-boot, linux, buildroot, openocd
saxon_clone

# Build the FPGA bitstream
saxon_standalone_compile bootloader CFLAGS_ARGS="-DSDRAM_TIMING=AS4C32M16SB_7TCN_ps"
SDRAM_SIZE=64 saxon_netlist
FPGA_SIZE=85 saxon_bitstream

# Build the firmware
saxon_opensbi
saxon_uboot
saxon_buildroot

# Build the programming tools
saxon_standalone_compile sdramInit CFLAGS_ARGS="-DSDRAM_TIMING=AS4C32M16SB_7TCN_ps"
saxon_openocd

Copy generated bitstream

dpavlin@klin:/klin/FPGA/saxonsoc$ cp SaxonSoc/hardware/synthesis/radiona/ulx3s/smp/bin/toplevel.bit saxon.bit
dpavlin@klin:/klin/FPGA/saxonsoc$ gzip -9 saxon.bit

Transfer it using ftp

ftp> put saxon.bit.gz
local: saxon.bit.gz remote: saxon.bit.gz
200 OK
150 Opened data connection.
226 Done.
359484 bytes sent in 10.27 secs (34.1994 kB/s)
ftp> site saxon.bit.gz

u-boot will fail to boot if you have rootfs on second partition

SDRAM init
OpenSBI copy
U-Boot copy
OpenSBI boot

OpenSBI v0.6-8-gd7b62b8
   ____                    _____ ____ _____
  / __ \                  / ____|  _ \_   _|
 | |  | |_ __   ___ _ __ | (___ | |_) || |
 | |  | | '_ \ / _ \ '_ \ \___ \|  _ < | |
 | |__| | |_) |  __/ | | |____) | |_) || |_
  \____/| .__/ \___|_| |_|_____/|____/_____|
        | |
        |_|

Platform Name          : VexRiscv SMP simulation
Platform HART Features : RV32AIMS
Platform Max HARTs     : 4
Current Hart           : 0
Firmware Base          : 0x80f80000
Firmware Size          : 84 KB
Runtime SBI Version    : 0.2

MIDELEG : 0x00000222
MEDELEG : 0x0000b101


U-Boot 2020.07-08304-gd361dd3997 (Sep 05 2020 - 09:45:52 +0200)

DRAM:  32 MiB
MMC:   spi@10020000:mmc@1: 0
Loading Environment from FAT... Unable to use mmc 0:1... In:    serial@10010000
Out:   serial@10010000
Err:   serial@10010000
Net:   No ethernet found.
Hit any key to stop autoboot:  0
Wrong Image Format for bootm command
ERROR: can't get kernel image!
=>

https://github.com/dok3r/ulx3s-saxonsoc/wiki/SaxonSoc-on-ULX3s

setenv bootcmd "load mmc 0:1 0x80000000 /boot/uImage;load mmc 0:1 0x80FF0000 /boot/dtb;fdt add 0x80FF0000;fdt memory 0x80000000 0x04000000;bootm 0x80000000 - 0x80FF0000"
setenv bootargs "rootwait console=hvc0 root=/dev/mmcblk0p2 init=/sbin/init mmc_core.use_spi_crc=0"
saveenv

Lawrie Griffiths @lawrie Sep 01 21:59

The new SaxonSoc is now working on a 12F for me. Here are the instructions to build from source - https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.1/bsp/radiona/ulx3s/smp
The images and bitstream are here - https://github.com/lawrie/saxonsoc-ulx3s-bin/tree/master/Smp
There is no sdcard image at the moment, but all the files are there for you to build your own.

ov7670 pmod

https://github.com/goran-mahovlic/fpga-odysseus/tree/master/projects/OV7670-HDMI

pmod pin mapping:

https://github.com/goran-mahovlic/fpga-odysseus/blob/master/projects/OV7670-HDMI/ulx3s.lpf#L335

SCCB Pullup Resistors

from https://github.com/westonb/OV7670-Verilog

The SCCB interface for the camera requires pull up resistors. You need to solder 4.7K resistors from the SIOD and SIOC pins on the camera to the 3.3V supply. You can do this yourself or have the staff in the EDS help you.

csi

https://twitter.com/mad_archer_/status/1231249513509261313

https://github.com/libv/fosdem-video-linux

litex

(just links, need to test it)

spiram

https://gitter.im/ulx3s/Lobby?at=5ef22d4c54d7862dc4a42395

@Speccery thereis also commandline "spiram.py" for some low-level inspection, so to reset TI this works for me

spiram.poke(0x100008,bytearray(0xFC))
spiram.poke(0x100008,bytearray(0xFF))

and to read bytes

spiram.peek(0,16)

bytearray(b'\x83\xe0\x00$\x83\xc0\t\x00\x83\xc0\n\x920\xaa\x04`')

led

ftx_prog --cbus 3 DRIVE_0 # green OFF

ftx_prog --cbus 3 SLEEP # green ON if enumerated

This is active after power cycle

micropython blue led

>>> from machine import Pin
>>> led=Pin(5,Pin.OUT)
>>> led.on() # upali plavu
>>> led.off() # ugasi plavu

micropython

from upysh import *


TODO

try various projects for ulx3s

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Type-C Station 10 in 1

Markings on packaging:

poa5788067

skud49610

Features:

Support USB Type-C DisplayPort Alt Mode.
The standard USB-C interface supports forward and backward insertion.
Support PD charging function power up to 60W (5~20V/3A Only charging) Max.
Port use black rubber core + nickel plated shell.
Adopt standard USB-A interface.
Comply with USB3.0 standard 5Gbps transmission.
Support reading and writing data, U disk, card reader, keyboard, mouse, mobile hard disk, solid state hard disk, digital camera, etc.
USB3.0 single port output power 4.5W (5V/0.9A) supports charging devices such as mobile phones.
Supports Micro SD (T-Flash) with standard TF card slot.
Transfer data using USB3.0 standard theory: 5Gbps.
Adopt standard SD card slot
Adopt standard HDMI-mother interface
Support audio and video transmission, video support up to 4Kx2K/30Hz and backward compatible
HDMI1.4
Support analog signal video transmission, video support 1920x1080/60Hz, 1920x1080K/30Hz and backward compatible
RJ45 port adopts imported RTL8153 chip and supports 10M/100M/1000M networks transmission.
Adopt four microphone headphone jacks.
Compliance with the standard (CTIA).
Mic audio recording and playback support 48K and 44.1K sampling rate.

Specification:

Material:Aluminum alloy
Color: Silver/Gray
Applicable models:
For MacBook Pro 2017 (13"& 15")
For MacBook Pro 2016 (13"& 15")
For MacBook 2015/2016
For ChromeBook Pixel
Laptop Computers Complying with USB-C Interface
Output: Type-C
Input interface:
1*HDMI interface
1*VGA interface
3*USB 3.0 Interface
1*RJ45 interface
1*3.5mm Audio Interface
1*Memory Card Interface
1*TF Card Interface
1*Mini DP interface
Network Interface: Gigabit
Video resolution:
HDMI: 4K (3840*2160), 30Hz downward compatible
VGA: 1920*1080, 60Hz downward compatibility
Working Voltage: 5V~20V
Working temperature: 0~45°

Package included:

1 x Adapter Hub

x1 dmesg

Connected to usb-c on Thinkpad x1

[330796.938562] usb 4-1.2: Failed to set U1 timeout to 0x0,error code -19
[330796.945207] usb 4-1.2: Set SEL for device-initiated U1 failed.
[330796.953401] usb 4-1.2: Set SEL for device-initiated U2 failed.
[330796.953405] usb 4-1.2: usb_reset_and_verify_device Failed to disable LPM
[330800.072541] usb usb4-port1: Cannot enable. Maybe the USB cable is bad?
[330800.072572] usb 4-1: USB disconnect, device number 2
[330800.072578] usb 4-1.2: USB disconnect, device number 3
[330800.074002] usb 4-1.3: USB disconnect, device number 4
[330800.074185] cdc_ether 4-1.3:2.0 enx0050b6b7e85b: unregister 'cdc_ether' usb-0000:3b:00.0-1.3, CDC Ethernet Device
[330800.109311] usb 4-1.4: USB disconnect, device number 5
[330820.716417] usb 1-3: new full-speed USB device number 10 using xhci_hcd
[330820.879114] usb 1-3: New USB device found, idVendor=177a, idProduct=963d, bcdDevice= 1.00
[330820.879125] usb 1-3: New USB device strings: Mfr=2, Product=3, SerialNumber=1
[330820.879130] usb 1-3: Product: Billboard Device
[330820.879135] usb 1-3: Manufacturer: EXPSM USB
[330820.879138] usb 1-3: SerialNumber: 0001
[330820.889606] hid-generic 0003:177A:963D.0003: hiddev0,hidraw0: USB HID v1.10 Device [EXPSM USB Billboard Device] on usb-0000:00:14.0-3/input0
[330822.128370] usb 1-3: USB disconnect, device number 10
[330824.552424] xhci_hcd 0000:3b:00.0: Timeout while waiting for setup device command
[330824.760580] usb 4-1: new SuperSpeed Gen 1 USB device number 6 using xhci_hcd
[330824.800393] usb 1-3: new high-speed USB device number 11 using xhci_hcd
[330824.888497] usb 4-1: new SuperSpeed Gen 1 USB device number 6 using xhci_hcd
[330824.972239] usb 1-3: New USB device found, idVendor=05e3, idProduct=0610, bcdDevice= 6.54
[330824.972246] usb 1-3: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[330824.972249] usb 1-3: Product: USB2.1 Hub
[330824.972251] usb 1-3: Manufacturer: GenesysLogic
[330824.975342] hub 1-3:1.0: USB hub found
[330824.979079] hub 1-3:1.0: 4 ports detected
[330825.233338] usb 4-1: new SuperSpeed Gen 1 USB device number 7 using xhci_hcd
[330825.255826] usb 4-1: New USB device found, idVendor=05e3, idProduct=0626, bcdDevice= 6.54
[330825.255837] usb 4-1: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[330825.255842] usb 4-1: Product: USB3.1 Hub
[330825.255846] usb 4-1: Manufacturer: GenesysLogic
[330825.257766] hub 4-1:1.0: USB hub found
[330825.258065] hub 4-1:1.0: 4 ports detected
[330825.312494] usb 1-3.3: new high-speed USB device number 12 using xhci_hcd
[330825.437770] usb 1-3.3: New USB device found, idVendor=05e3, idProduct=0618, bcdDevice=87.53
[330825.437780] usb 1-3.3: New USB device strings: Mfr=0, Product=1, SerialNumber=0
[330825.437785] usb 1-3.3: Product: USB2.0 Hub
[330825.439067] hub 1-3.3:1.0: USB hub found
[330825.439379] hub 1-3.3:1.0: 4 ports detected
[330825.544465] usb 4-1.4: new SuperSpeed Gen 1 USB device number 8 using xhci_hcd
[330825.565383] usb 4-1.4: New USB device found, idVendor=0bda, idProduct=8153, bcdDevice=30.00
[330825.565394] usb 4-1.4: New USB device strings: Mfr=1, Product=2, SerialNumber=6
[330825.565399] usb 4-1.4: Product: USB 10/100/1000 LAN
[330825.565403] usb 4-1.4: Manufacturer: Realtek
[330825.565406] usb 4-1.4: SerialNumber: 000001
[330825.608359] usbcore: registered new interface driver r8152
[330825.688848] usb 4-1.4: reset SuperSpeed Gen 1 USB device number 8 using xhci_hcd
[330825.728420] usb 1-3.3.1: new high-speed USB device number 13 using xhci_hcd
[330825.740964] r8152 4-1.4:1.0 eth0: v1.09.9
[330825.791038] r8152 4-1.4:1.0 enx00e04c6800e9: renamed from eth0
[330825.841409] usb 1-3.3.1: New USB device found, idVendor=05e3, idProduct=0752, bcdDevice= 2.33
[330825.841412] usb 1-3.3.1: New USB device strings: Mfr=3, Product=4, SerialNumber=0
[330825.841414] usb 1-3.3.1: Product: USB Storage
[330825.841415] usb 1-3.3.1: Manufacturer: Generic
[330825.843667] usb-storage 1-3.3.1:1.0: USB Mass Storage device detected
[330825.843985] scsi host1: usb-storage 1-3.3.1:1.0
[330826.857820] scsi 1:0:0:0: Direct-Access     Generic  STORAGE DEVICE   0233 PQ: 0 ANSI: 0
[330826.858611] sd 1:0:0:0: Attached scsi generic sg1 type 0
[330826.860029] sd 1:0:0:0: [sdb] Attached SCSI removable disk
[330839.531138] usb 1-3: USB disconnect, device number 11
[330839.531149] usb 1-3.3: USB disconnect, device number 12
[330839.531154] usb 1-3.3.1: USB disconnect, device number 13
[330840.284381] usb 4-1: USB disconnect, device number 7
[330840.284392] usb 4-1.4: USB disconnect, device number 8

x230 dmesg

Connected using usb-c to usb 3 adapter (no video adapter if not connected using usb-c?)

[Sat Aug 29 13:14:26 2020] xhci_hcd 0000:00:14.0: Timeout while waiting for setup device command
[Sat Aug 29 13:14:32 2020] xhci_hcd 0000:00:14.0: Timeout while waiting for setup device command
[Sat Aug 29 13:14:32 2020] usb 3-2.4: device not accepting address 6, error -62
[Sat Aug 29 13:14:32 2020] usb 2-2.4: new high-speed USB device number 10 using xhci_hcd
[Sat Aug 29 13:14:32 2020] usb 2-2.4: New USB device found, idVendor=05e3, idProduct=0610, bcdDevice= 6.54
[Sat Aug 29 13:14:32 2020] usb 2-2.4: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[Sat Aug 29 13:14:32 2020] usb 2-2.4: Product: USB2.1 Hub
[Sat Aug 29 13:14:32 2020] usb 2-2.4: Manufacturer: GenesysLogic
[Sat Aug 29 13:14:32 2020] hub 2-2.4:1.0: USB hub found
[Sat Aug 29 13:14:32 2020] hub 2-2.4:1.0: 4 ports detected
[Sat Aug 29 13:14:32 2020] usb 3-2.4: new SuperSpeed Gen 1 USB device number 7 using xhci_hcd
[Sat Aug 29 13:14:33 2020] usb 3-2.4: New USB device found, idVendor=05e3, idProduct=0626, bcdDevice= 6.54
[Sat Aug 29 13:14:33 2020] usb 3-2.4: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[Sat Aug 29 13:14:33 2020] usb 3-2.4: Product: USB3.1 Hub
[Sat Aug 29 13:14:33 2020] usb 3-2.4: Manufacturer: GenesysLogic
[Sat Aug 29 13:14:33 2020] hub 3-2.4:1.0: USB hub found
[Sat Aug 29 13:14:33 2020] hub 3-2.4:1.0: 4 ports detected
[Sat Aug 29 13:14:33 2020] usb 2-2.4.3: new high-speed USB device number 11 using xhci_hcd
[Sat Aug 29 13:14:33 2020] usb 2-2.4.3: New USB device found, idVendor=05e3, idProduct=0618, bcdDevice=87.53
[Sat Aug 29 13:14:33 2020] usb 2-2.4.3: New USB device strings: Mfr=0, Product=1, SerialNumber=0
[Sat Aug 29 13:14:33 2020] usb 2-2.4.3: Product: USB2.0 Hub
[Sat Aug 29 13:14:33 2020] hub 2-2.4.3:1.0: USB hub found
[Sat Aug 29 13:14:33 2020] hub 2-2.4.3:1.0: 4 ports detected
[Sat Aug 29 13:14:33 2020] usb 3-2.4.4: new SuperSpeed Gen 1 USB device number 8 using xhci_hcd
[Sat Aug 29 13:14:33 2020] usb 3-2.4.4: New USB device found, idVendor=0bda, idProduct=8153, bcdDevice=30.00
[Sat Aug 29 13:14:33 2020] usb 3-2.4.4: New USB device strings: Mfr=1, Product=2, SerialNumber=6
[Sat Aug 29 13:14:33 2020] usb 3-2.4.4: Product: USB 10/100/1000 LAN
[Sat Aug 29 13:14:33 2020] usb 3-2.4.4: Manufacturer: Realtek
[Sat Aug 29 13:14:33 2020] usb 3-2.4.4: SerialNumber: 000001
[Sat Aug 29 13:14:33 2020] usb 3-2.4.4: reset SuperSpeed Gen 1 USB device number 8 using xhci_hcd
[Sat Aug 29 13:14:33 2020] r8152 3-2.4.4:1.0: firmware: failed to load rtl_nic/rtl8153a-4.fw (-2)
[Sat Aug 29 13:14:33 2020] r8152 3-2.4.4:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
[Sat Aug 29 13:14:33 2020] r8152 3-2.4.4:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
[Sat Aug 29 13:14:33 2020] r8152 3-2.4.4:1.0 eth0: v1.11.11
[Sat Aug 29 13:14:33 2020] r8152 3-2.4.4:1.0 enx00e04c6800e9: renamed from eth0
[Sat Aug 29 13:14:33 2020] usb 2-2.4.3.1: new high-speed USB device number 12 using xhci_hcd
[Sat Aug 29 13:14:33 2020] usb 2-2.4.3.1: New USB device found, idVendor=05e3, idProduct=0752, bcdDevice= 2.33
[Sat Aug 29 13:14:33 2020] usb 2-2.4.3.1: New USB device strings: Mfr=3, Product=4, SerialNumber=0
[Sat Aug 29 13:14:33 2020] usb 2-2.4.3.1: Product: USB Storage
[Sat Aug 29 13:14:33 2020] usb 2-2.4.3.1: Manufacturer: Generic
[Sat Aug 29 13:14:33 2020] usb-storage 2-2.4.3.1:1.0: USB Mass Storage device detected
[Sat Aug 29 13:14:33 2020] scsi host6: usb-storage 2-2.4.3.1:1.0
[Sat Aug 29 13:14:34 2020] scsi 6:0:0:0: Direct-Access     Generic  STORAGE DEVICE   0233 PQ: 0 ANSI: 0
[Sat Aug 29 13:14:34 2020] sd 6:0:0:0: Attached scsi generic sg2 type 0
[Sat Aug 29 13:14:34 2020] sd 6:0:0:0: [sdc] Attached SCSI removable disk

firmware for network card

root@x230:/home/dpavlin# apt install firmware-realtek

dpavlin@x230:/lib/firmware$ ls -al rtl_nic/rtl8153a-4.fw
ls: cannot access 'rtl_nic/rtl8153a-4.fw': No such file or directory

sigh, if package is too old here is work-around: https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=962972

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TC358743XBG

Board name: H2C-RPI-B01

HDMI interface to CSI-2 interface
Chip: TC358743XBG
Support TK1 full-featured expansion board
Support Raspberry Pi (linux kernel version to 4.0 or above)
Limited by the performance of Raspberry itself, up to 1080p@25
Physical size: 65x30 mm, fixed hole position is the same as zero.

https://www.aliexpress.com/item/4000152180240.html

https://www.raspberrypi.org/forums/viewtopic.php?f=38&t=120702&start=400#p1339178

Lusya Upgraded version Raspberry Pi HDMI Adapter Board HDMI interface to CSI-2 TC358743XBG for 4B 3B 3B+ ZERO G11-011

[    8.590920] tc358743 0-000f: tc358743 found @ 0x1e (bcm2835 I2C adapter)

root@pihdmi:/home/pi/CSI2_device_config# git remote -v
origin	https://github.com/6by9/CSI2_device_config (fetch)
origin	https://github.com/6by9/CSI2_device_config (push)

root@pihdmi:/home/pi/CSI2_device_config# cat edid.sh
v4l2-ctl --set-edid=file=1080P50EDID.txt --fix-edid-checksums

root@pihdmi:/home/pi/CSI2_device_config# sh -x edid.sh
+ v4l2-ctl --set-edid=file=1080P50EDID.txt --fix-edid-checksums

CTA-861 Header
  IT Formats Underscanned: yes
  Audio:                   yes
  YCbCr 4:4:4:             no
  YCbCr 4:2:2:             no

HDMI Vendor-Specific Data Block
  Physical Address:        3.0.0.0
  YCbCr 4:4:4 Deep Color:  no
  30-bit:                  no
  36-bit:                  no
  48-bit:                  no

CTA-861 Video Capability Descriptor
  RGB Quantization Range:  yes
  YCC Quantization Range:  no
  PT:                      Supports both over- and underscan
  IT:                      Supports both over- and underscan
  CE:                      Supports both over- and underscan


https://fluxcoil.net/hardwarerelated/raspberry_pi_4_tc358743

H5a650680b5f549749cce0a1a1f258bc2d.png

Hf9554fe5db464123bc629f548d89b606S.jpg
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Exynos

Spin-off from Chromebook papge to document running mainline u-boot and Linux on Exynos



u-boot

SPI eeprom image

dpavlin@klin:/klin/u-boot$ cat build-spi.sh 
#!/bin/sh -xe

make
#cp /klin/books/Chromebook/spi/snow-bricked.rom .
cp snow-bricked.rom snow-mix.rom
dd conv=notrunc if=spl/smdk5250-spl.bin of=snow-mix.rom seek=$((0x00002000)) bs=1
dd conv=notrunc if=u-boot.bin of=snow-mix.rom seek=$((0x00006000)) bs=1
scp snow-mix.rom rpi2:chromebook/


Upstream u-boot works, but can't find mmc devices, so internal flash is not accessable, so I had to boot from USB network using u-boot pxe

chromiumos build

dpavlin@klin:/klin/chromebook$ . env.sh 
dpavlin@klin:/klin/chromebook/chromiumos$ cros_sdk

  • apply some patches (or not) as described at
(cr) (altAddr) dpavlin@klin ~/trunk/src/third_party/u-boot/files $ emerge-${BOARD} chromeos-u-boot



pxelinux config

dpavlin@x230:/var/tftp/pxelinux.cfg$ cat default-arm-exynos 
TIMEOUT 10

MENU TITLE TFTP boot

LABEL snow
        MENU LABEL sdcard?
        LINUX ../zImage
        FDTDIR ../
        APPEND console=tty1 console=ttyS0,115200n8 loglevel=8 rootwait rw earlyprintk root=/dev/sdcard0


kernel

doesn't boot ATM

dpavlin@klin:/klin/imx6/linux-imx$ cat build-chromebook.sh 
# 

cd /klin/chromebook/chromiumos/src/third_party/kernel/v4.4

export CROSS_COMPILE="arm-linux-gnueabihf-" ARCH=arm

test ! -f .config && make exynos_defconfig
make -j4 zImage exynos5250-snow.dtb
cp -v arch/arm/boot/zImage arch/arm/boot/dts/exynos5250-snow.dtb /media/boot/


chromiumos kernel

https://github.com/dnschneid/crouton/wiki/Build-chrome-os-kernel-and-kernel-modules

security

(might not be related, but useful to keep track of)

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ESP32CAM


connection, flashing

connected to pl2303 serial

pl2303 esp32cam
3v3 not connected
rxd UnR
rxd UOT
gnd GND
5v 5V

ESP32-CAM-pinout-new.png

To program the board, I userd jumper to jump GPIO0 with GND pin next to it.

timelapse

old, obsolete problems

It seems that my module is usually known as AI thinker variant. It has terrible picture which starts with huge green bias.

It also doesn't work for me in resolutions below 1024x768 (in current esp32 example as of 2019-08-02).

Plugging it into external 5V power supply did not helped much.


To solve green tint, I just left esp32cam module plugged in whole day and night. I guess that image sensor got discharged during night, but next day picture was fine.

Problem with image resolution was fixed by updating to more recent version of ESP32 support for Arduino (as of 2020-04-20 it works fine)

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DSO150
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