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ESP32CAM


https://github.com/raphaelbs/esp32-cam-ai-thinker/blob/master/docs/about-esp32-cam.md

connection, flashing

connected to pl2303 serial

pl2303 esp32cam
3v3 not connected
rxd UnR
rxd UOT
gnd GND
5v 5V

ESP32-CAM-pinout-new.png

To program the board, I userd jumper to jump GPIO0 with GND pin next to it.

improved example app

https://github.com/easytarget/esp32-cam-webserver

   cp myconfig.sample.h myconfig.h
   vi myconfig.h
dpavlin@nuc:/nuc/esp32/esp32-cam-webserver$ platformio run

dpavlin@nuc:/nuc/esp32/esp32-cam-webserver$ pio run -t upload --upload-port /dev/ttyUSB2
"/home/dpavlin/.platformio/penv/bin/python" "/home/dpavlin/.platformio/packages/tool-esptoolpy/esptool.py" \
--chip esp32 --port "/dev/ttyUSB3" --baud 460800 --before default_reset --after hard_reset \
write_flash -z --flash_mode dio --flash_freq 40m --flash_size detect \
0x1000 /home/dpavlin/.platformio/packages/framework-arduinoespressif32/tools/sdk/bin/bootloader_dio_40m.bin \
0x8000 /nuc/esp32/esp32-cam-webserver/.pio/build/esp32cam/partitions.bin \
0xe000 /home/dpavlin/.platformio/packages/framework-arduinoespressif32/tools/partitions/boot_app0.bin \
0x10000 .pio/build/esp32cam/firmware.bin

timelapse

ocr on device

https://github.com/jomjol/AI-on-the-edge-device

https://github.com/jomjol/AI-on-the-edge-device/wiki/Installation

Remove glue from lens (very hard, using sharp knife), and rotate lens by 45 degrees until
picture is sharp (I had to use pliers to do this).

dpavlin@nuc:/nuc/esp32/AI-on-the-edge-device$ vi sd-card/wlan.ini

dpavlin@nuc:/nuc/esp32/AI-on-the-edge-device/code$ pio run

dpavlin@nuc:/nuc/esp32/AI-on-the-edge-device/code$ pio run -v -t upload --upload-port /dev/ttyUSB3

"/home/dpavlin/.platformio/penv/bin/python" "/home/dpavlin/.platformio/packages/tool-esptoolpy/esptool.py" \
--chip esp32 --port "/dev/ttyUSB3" --baud 460800 --before default_reset --after hard_reset \
write_flash -z --flash_mode dio --flash_freq 40m --flash_size detect \
0x1000 /nuc/esp32/AI-on-the-edge-device/code/.pio/build/esp32cam/bootloader.bin \
0x8000 /nuc/esp32/AI-on-the-edge-device/code/.pio/build/esp32cam/partitions.bin \
0xd000 /nuc/esp32/AI-on-the-edge-device/code/.pio/build/esp32cam/ota_data_initial.bin \
0x10000 .pio/build/esp32cam/firmware.bin

# original flashing instructions
esptool write_flash 0x01000 bootloader.bin 0x08000 partitions.bin 0x10000 firmware.bin

# download raw picture
wget 192.168.3.112/img_tmp/raw.jpg



old, obsolete problems

It seems that my module is usually known as AI thinker variant. It has terrible picture which starts with huge green bias.

It also doesn't work for me in resolutions below 1024x768 (in current esp32 example as of 2019-08-02).

Plugging it into external 5V power supply did not helped much.


To solve green tint, I just left esp32cam module plugged in whole day and night. I guess that image sensor got discharged during night, but next day picture was fine.

Problem with image resolution was fixed by updating to more recent version of ESP32 support for Arduino (as of 2020-04-20 it works fine)

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ULX3S Lobby

Helpful notes from chat about ULX3S

Contents: [Dobrica Pavlinušić's random unstructured stuff]


i2c

https://gitter.im/ulx3s/Lobby?at=5dfcf29acf771f7708ff69e9

It should not be that hard. I have i2c in SaxonSoc in other projects such as https://github.com/SpinalHDL/SaxonSoc/blob/dev/hardware/scala/saxon/board/blackice/BlackiceSocArduino.scala#L25

The generated board support packages include a generated dts, but it is not used yet and the simple i2c generator that I wrote does not generate the dts.

There is a problem building SaxonSoc Linux, that some build randomly do not work. It seems to be something to do with SDRAM access.

@Dolu1990 is about to redo the SDRAM access for the Ulx3s, which should make it more reliable and faster, as he plans to support double frequency access.

There is a lot of information on the development of the u-boot version here , which might be useful to you - SpinalHDL/SaxonSoc#7

https://github.com/SpinalHDL/SaxonSoc/pull/7

I2c Linux support will also need a spinal.lib driver here - https://github.com/SpinalHDL/linux/tree/linux-5.0.y/drivers/i2c

The terasic De1Soc version of SaxonSoc Linux has a dts entry for an led for disk access - https://github.com/SpinalHDL/buildroot/blob/saxon/board/spinal/saxon_default/spinal_saxon_default_de1_soc.dts#L194

We really need a better GPIO mapping for the Ulx3s. That might involve including adding a second gpio peripheral to the hardware (gpioB) and doing a better lpf file mapping to pins. It might mean increasing the niumbers of pins that support interrupts. It would be good to include access to the buttons and switches and to make it easy to add Pmods that need interrupt support like the enc28j60 one.

ecp5pll

Mario Hoffmann @hoffma_gitlab Aug 05 16:11

Hello, I wanted to have a 90 degree shifted clock. I was trying out the ecp5pll from @emard. I get it running and the clock adjustment seems to work, but somehow it does not get shifted for me. Is this currently not working with yosys and so forth, is there anything I have to take care of, or might it just be a bug on my side? Tried to search this chat a bit and just searched a bit on the internet but the things I found about it were quite old and not necessarily about my problem. Any ideas? I am using the vhdl version btw

emard @emard Aug 05 16:59

There's some order of signals and small delays between them for dynamic shifting to work. https://github.com/emard/ulx3s-misc/blob/master/examples/sdram/memtest_mister/hdl/top/top_memtest.v#L73 here is module to control phase shifts by pressing of BTN for testing of SDRAM with variable phase shift of the clock to chip

Mario Hoffmann @hoffma_gitlab Aug 05 17:01

alright, ill look at that. thanks

Mario Hoffmann @hoffma_gitlab Aug 05 17:53

Oh nice it works. My thinking was just a bit wrong and there was a little bug too. Thanks

emard @emard Aug 05 18:07

ecp5pll has possibility for fine-precision phase adjustment but this simple BTN module doesn't generate proper phaseloadreg signal https://github.com/emard/ulx3s-misc/blob/master/examples/sdram/memtest_mister/hdl/btn_ecp5pll_phase.v#L51

display

https://gitter.im/ulx3s/Lobby?at=5f3b7df7ee58011680b36cb0

emard @emard Aug 18 09:06

SSD1331 96x64 is full featured OLED beautiful contrast, but currently best buy is ST7789 1.3" 240x240 LCD less contrast but more pix and less $. Do not solder directly the display. Solder female 7-pin header and plug the display. Mechanical stabilization can be 3D printed https://github.com/emard/ulx3s/tree/master/box it will "work" properly only if whole box is printed. There is no problem with heat normally to FPGA but SSD1331 with wrong software commands can become hot to fry fingers and smoke, it happened to me once, colors faded and I just replaced display. Onboard USB-SERIAL can provide 2nd JTAG channel for openocd debugger of RISCV processor it will work but it will be VERY slow (for debug single step ok, but for transferring Mbps no).

rtc

https://gitter.im/ulx3s/Lobby?at=5f3b86a1a8c178017657caf6

emard @emard Aug 18 09:43

Yes for RTC I first saw it "works" but after few reboots I found out that it resets to compile time or something. Core could consult onboard RTC using i2c and then set unix time integer counter which will continue ticking afterwards. For setting RTC we have esp32 and other options. Btw import ntptime; ntptime.settime() will set ESP32 localtime() from a pool of network NTP servers and then esp32 can initialize onboard RTC here I have played with this https://github.com/emard/ulx3s-misc/tree/master/examples/rtc/micropython-mcp7940n/esp32

https://gitter.im/ulx3s/Lobby?at=5f3dbb34750a2741302ea427

emard @emard Aug 20 01:52

@pnru_gitlab here is 8-bit master interface. I haven't tested it very simple by reading seconds and seems ok https://github.com/emard/ulx3s-misc/blob/master/examples/rtc/i2c_master/proj/hdl/i2c_master_8bit.v

https://gitter.im/ulx3s/Lobby?at=5f3e2d1c07c30d132a9c4f58

emard @emard Aug 20 09:58

when we are at verilog, I have found on the net several i2c bidirectional bridges. Only one code worked at our board but it works only if compiled by diamond. trellis compiles but doesn't work. Can someone take a look what I have missed: bridge: https://github.com/emard/ulx3s-misc/blob/master/examples/rtc/micropython-mcp7940n/proj/hdl/i2c_bridge.v toplevel usage: https://github.com/emard/ulx3s-misc/blob/master/examples/rtc/micropython-mcp7940n/proj/top/top_i2c_bridge.v

emard @emard Aug 20 22:04

for me it works for any gpdi_scl/sda PULLMODE=UP, DOWN, or NONE so it's not pull setting. I can prepare a bitstream and micropython to ulx3s-bin example that initializes the clock setting time from NTP

emard @emard Aug 20 22:18

https://github.com/emard/ulx3s-bin/tree/master/esp32/micropython/rtc can you try this RTC esp32 example for NTP setting? >>> rtcdemo.mcp.time should advance seconds

emard @emard Aug 21 00:04

RTC traffic also appears at GPDI connector (if there's i2c chip 3.3V->5V adapter soldered on board PCA9306D). Some monitors may hold i2c lines. Also gpdi connector can be used to monitor traffic if e.g. you have hdmi breakout board
If you don't have battery, RTC will keep setting until board is powered off
If you have 2 ULX3S boards and mini-display OLED/LCD, you can connect 2 ULX3S together and on one run scopeio, which will monitor the other i2c traffic
I can prepare scope stuff for such setup because scopeio is vhdl, advanced so much that ghdl won't have chance in near future to compile it

emard @emard Aug 21 00:09

UPS but we have problem there will be 2 RTC chips colliding address :)
about i2c master 8bit. First write highest bytes 3,2,1 (order not important) and last write byte 0, this should initiate i2c transaction. byte 3=0x80 is READ, byte 3=0x00 is write
If you write 0x00 to register 0x00 (seconds) it will stop RTC. To start, it needs 0x80 written to 0x00 (MSB bit must be set) then the RTC should start "ticking"

emard @emard Aug 21 18:14

I fixed i2c_bridge.v to work with both trellis and diamond.

Paul Ruiz @pnru_gitlab Aug 21 23:35

Which way does the battery go? I think with the + side (cap) up and the - side (ribbed) to the PCB?
@emard: thanks for all the links, but your code already appears to work. The long one is interesting, it uses the same two level state machine idea that my non-working i2c controller uses.

emard @emard Aug 21 23:59

Battery goes + up (larger part of battery should be in contact with metallic holder soldered) - down (smaller part of battery in contact to big circular pad on the PCB
Glad to hear good news that my code works - it hasn't been tested on real CPU but I made some BTNs toplevel and a read and write to register 0 worked

scopeio

https://gitter.im/ulx3s/Lobby?at=5f3c27ffa05e464346d2f6ea

emard @emard Aug 18 21:11

@gkankanh MAX11125 is 1Msa/s total so e.g. if you use 4ch then each channel will be 0.25MSa/s per channel. For oscilloscope it, we have ready solution at hdl4fpga/ULX3S/scopeio you will see traces on monitor. For analysis, onboard USB-serial can do 3Mbps so it could be nearly useable. For faster ADC, yes 100 Mbit ethernet ETH8720 from ebay, module for 2.2$ and for example ebay's AN108 AD/DA module 32MSa/s input, 125MSa/s output https://www.ebay.com/itm/ADDA-Module-Data-Signal-Acquisition-High-speed-Directly-pluggable-connector-/253556250998 also scopeio supports it

how to solder headers

https://gitter.im/ulx3s/Lobby?at=5f3cd88378f4a801801336cb

emard @emard Aug 19 09:45

To have GP/GN not be swapped from "default" design, Either solder 90° FEMALE headers on top side of board (nice for PMODs directly) or straight 0° MALE pins down on bottom side of board. PMODs can also plug to other end of flat cable and pinout will be identical as if 90° was soldered onboard.

nmingen

https://gitter.im/ulx3s/Lobby?at=5f3cfbce8b8d4f633effcea7

Lawrie Griffiths @lawrie Aug 19 12:15

I am using Ubuntu 20.04, so I need to use pip3 not pip. (You can't get python2 pip on 20.04 easily).
The installation instructions for nmgen-boards says "Todo", so I installed it like the m_labs version said.
I changed the blinky example to use ULX3S_85F_Platform and ran that. It complained that tool {} was missing.
It seemed that it needed OpenFpgaLoader for upload, so I installed that, and then the blinky worked.

from nmigen import *
from nmigen_boards.ulx3s import *


class Blinky(Elaboratable):
    def elaborate(self, platform):
        led   = platform.request("led", 0)
        timer = Signal(26)

        m = Module()
        m.d.sync += timer.eq(timer + 1)
        m.d.comb += led.o.eq(timer[-1])
        return m


if __name__ == "__main__":
    platform = ULX3S_85F_Platform()
    platform.build(Blinky(), do_program=True)

https://github.com/GuzTech/ulx3s-nmigen-examples

https://github.com/greatscottgadgets/luna

SDRAM memtest

https://gitter.im/ulx3s/Lobby?at=5f4ea96249a1df0a12c0d83e

Lawrie Griffiths @lawrie Sep 01 22:04

@pnru_gitlab @Dolu1990 asked these questions about using the SDRAM, which I thought you might know something about from all your recent work on SDRAM drivers:
I'm thinking about the SDRAM
currently, the soc is at 50 mhz, and the sdram run at 100 Mhz using DDR io
but maybe we should quad pump the SDRAM, and doing some bootloader calibration to ajust read delays
i'm just currently not sure what is the critical path of the SDRAM chip themself
in other words "why they are specified to X frequancy and not more"

Dolu1990 @Dolu1990 Sep 01 22:05

Moaaaar powaaaaaaaa

emard @emard Sep 01 22:36

oooh yeea :)) if you want to push SDRAM near the edge and give it some heat, on selected designs it can push 133MHz chips to 180-200 MHz, fmax depends on each board. 12F performs better than 85F. Here's memtest https://github.com/emard/ulx3s-misc/tree/master/examples/sdram/memtest_mister shows results on DVI monitor and with BTNs can adjust phase shift dynamically and watch for errors.

Dolu1990 @Dolu1990 Sep 01 23:01

<3
Nice thanks :)
So this test controle the shift of the clock sent to the DRAM ?
(it doesn't use the programable input delay ?)

emard @emard Sep 01 23:08

Yes this has a classic sdram driver that normally needs 90° phase offset to chip hardware, but as fmax is getting higher the actual phase shift which makes it really work moves. PLL is used to provide phase shift. Paul has made a better sdram driver with cool vendor-independent delay solution with a number of NOT gates.Only ns delay per NOT gate remains vendor dependent

Dolu1990 @Dolu1990 Sep 01 23:09

ok :D

Paul Ruiz @pnru_gitlab 00:02

@lawrie @Dolu1990 I am not sure I understand the SDRAM questions. In any case, my latest version is here: https://gitlab.com/pnru/cortex/-/blob/master/sdram.v
In particular note new lines 45-47 - I am not sure why, but this mod generally pushes Fmax up to about 200MHz (it depends a bit on the NextPNR seed).

I am not sure what you mean by "using DDR io" - does the SDRAM chip on the ULX3S support DDR? Maybe you mean by DDR that it runs at twice the speed of the CPU or that it uses burst size 2?

I don't know what the critical path in the SDRAM chip is, but I do have a hypothesis. When working with a CAS delay of 3 clocks, the data really arrives after 2 clocks plus 6-7ns (spending on the speed grade). If you clock a grade 6 chip (PC166) faster, a clock cycle will take less than 6ns and the data will only arrive after the third rising clock edge. My guess is that the 6-7ns is related to the speed of the sense amplifiers or something like that.

resource utilization

https://gitter.im/ulx3s/Lobby?at=5f4f8c30d4f0f55ebbf93007

Dolu1990 @Dolu1990 Sep 02 14:12

Is somebody aware of a way to get hearchical ressource utilisation report out from yosys/next-pnr for ECP5 ?
Basicaly, trying to nail down the ressource usage

David Shah @daveshah1 Sep 02 14:18

You can get a hierarchical report with Yosys by passing -noflatten to synth_ecp5

ps2 keyboard

https://gitter.im/ulx3s/Lobby?at=5f57e59c59ac794e02f71d14

Kid CUDA @KidCUDA_gitlab Sep 08 22:12

anyone used a PS2 keyboard with ULX3S?
like a proper PS2 keyboard with the pins adapted to USB?
is a level shifter needed or is the USB port 5V-data-tolerant?
from the schematic it doesn't look 5V tolerant but I'm not sure how else it would work with just a pure PS2 adapter as suggested in the docs

emard @emard Sep 08 22:52

@KidCUDA_gitlab US2 pins are 5V tolerant, limited by R and Zener diodes. Still some PS/2 keyboards don't accept 3.3V levels. Best is to obtain combo PS/2+USB they usually work in both modes for ULX3S
PS/2 is normally used over OTG connector for most of our retro-computing cores, apple1-2, ti99, zx, vic20, QL just to name a few

cortex

source: https://gitlab.com/pnru/cortex

https://gitter.im/ulx3s/Lobby?at=5f500a7eec534f584fdbeb15

Paul Ruiz @pnru_gitlab Sep 02 23:11

    8s is super-comfortable! Btw I wonder how did cortex start, before it ever booted they need some filesystem to hold files. Is cortex filesystem mountable by modern linux? How did they made it in early times?

The Cortex was a traditional home computer with Basic in its day. Running Unix on it was my project some 6-7 years ago. It was a long journey: porting a C compiler and tool chain, building simple kernels with a linked in user program (downloaded to the H/W via something similar to S-records), etc. When the time for disk access came, I used a tool to create & manage disk images.

For the original Unix, the file system was almost the first thing that was built, after the assembler (that is how a.out got its name: assembler output). An empty disk image was written by a custom format program. Files were then loaded from paper tape. Some 1969/1970 Unix code can be found here:
https://www.tuhs.org/cgi-bin/utree.pl
In its first incarnations it was all assembler, but many of the core ideas were already there. Some more background is here:
https://www.bell-labs.com/usr/dmr/www/hist.html

emard @emard Sep 02 23:14

Ahaaaa so unix was not all the time available on cortex hardware. Still I'd wanted to know how did you initially start with populated filesystem. Normally e.g. if we have linux on riscv, we can mount the same partition on x86 PC, copy files and and it will work on riscv, but how was this done on cortex?

So If I understood, you have a tool that from a directory creates disk image, but there's currently no support to actually mount cortex fs on linux for example. linux has some possibility to write a user-space fs driver like "fuse" but I ghess thats difficult and fragile

Paul Ruiz @pnru_gitlab Sep 02 23:29

You can follow my journey here, in 315 commits:
https://www.jslite.net/cgi-bin/9995/timeline?n=400&y=all&v=0

I use a program ("ufs") which creates a disk image from scratch and then adds files to it. The source code is here:
https://www.jslite.net/cgi-bin/9995/dir?ci=84b2a75947eb76db&name=fsutil

Even on the mini Cortex hardware, the CF Card uses FAT formatting and has an image file on it. I make sure the image is contiguous and the boot loader lets the Unix disk driver know in which sector the image starts. This way I can simply copy disk images to the CF card without needing to use special tools.

Actually, the card also has disk images for other OS's as well - MDEX and NOS, which are somewhat similar to CP/M and MS-DOS 3 respectively.

emard @emard Sep 02 23:44

There has been a lot of concentrated effort! The idea to use contiguous file in FAT is very good, so the CF itself can be easily written from laptop.

Paul Ruiz @pnru_gitlab Sep 02 23:53

Thank you. The ulx3s Cortex has it even easier: because of the ESP32, now I don't even have to worry about things being contiguous and I can ftp disk images without having to handle the SD card.

emard @emard Sep 03 00:34

yeees it was a piece of luck that for esp32 appeared good micropython support with almost all important things working and that spi-jtag adventure turned out successful. I have ulx3s with SD in a box and once inserted SD I never move out, just ftp files. Things will be even better when WROVER-E prototype starts working, 4MB RAM, 16MB FLASH no more out of memory. Bitstreams could be unzipped on-the-fly, even larger FLASH chips supported with 64K and 256K erase blocks (esp32 must buffer data size of erase block and now we are struggling with 4K buffers)

saxonsoc audio

https://gitter.im/ulx3s/Lobby?at=5f6482c3603d0b37f43d3ec0

Lawrie Griffiths @lawrie Sep 18 11:49

I have a 4-cpu 85F SaxonSoc version with music, working now.

It is now inSmp/bitstreams/ulx3s_85f_blue_4core_saxonsoc.bit
I renamed images as oldimages and the new one are in Smp/images.
You need dtb, uImage and you need to untar the new rootfs.tar.
You will also need:

root@buildroot:~# cat .asoundrc
pcm.!default {
    type            plug
    slave.pcm       "softvol"   #make use of softvol
}

pcm.softvol {
    type         softvol
    slave {
        pcm         "hw:0,0"      #redirect the output to dmix (instead of "hw:0,0")
    }
    control {
           name        "PCM"       #override the PCM slider to set the softvol volume level globally
        card     0
    }
}

To play music do: mpg123 -T -f 4096 -m file.mp3.
Or to play in the background nohup mpg123 -T -f 4096 -m file.mp3 &
It is set up for a 64MB blue 85f.

https://gitter.im/ulx3s/Lobby?at=5f648d8cf51808513b4f7db5

olu1990 @Dolu1990 Sep 18 12:35

.asoundrc isn't necessary, it just add volume controles in alsamixer app
I would suggest to not add the .asoundrc for single core versions, as it add quite a bit of overhead
the -m of mpg123 is for mono, if the mp3 bit rate isn't to high, it might be fine in stereo
(for single core)

saxonsoc rtc

https://gitter.im/ulx3s/Lobby?at=5f69eb5d6a6e094525ac61f5

https://gitter.im/ulx3s/Lobby?at=5f69f087e1dd7c19548aad12

Dolu1990 @Dolu1990 Sep 22 14:39

got the rtc to start counting seconds and read it via :

i2cset -y 0 0x6F 0x00 0x80
sleep 4
i2cget -y 0 0x6F 0x00

https://gitter.im/ulx3s/Lobby?at=5f6a4562e1dd7c19548b96f0

Lawrie Griffiths @lawrie Sep 22 20:41

oot@buildroot:~# cat date.sh 
R6=`i2cget -y 0 0x6f 0x06`
R5=`i2cget -y 0 0x6f 0x05`
R4=`i2cget -y 0 0x6f 0x04`
R2=`i2cget -y 0 0x6f 0x02`
R1=`i2cget -y 0 0x6f 0x01`

YY="${R6:2:2}"
MON="$((${R5:2:2}-20))"
DD="${R4:2:2}"
HH="${R2:2:2}"
MM="${R1:2:2}"

echo "20$YY-$MON-$DD $HH:$MM"
root@buildroot:~# ./date.sh 
2020-9-22 19:40

date -s "`./date.sh`"

https://gitter.im/ulx3s/Lobby?at=5f6a69588fe6f11963554984

emard @emard Sep 22 23:15

#include <stdio.h>
#include <stdlib.h>

#define I2C_SLAVE 0x703
#define O_RDWR 2

int i2c_rtc;

void rtc_open(int addr)
{
  i2c_rtc = open("/dev/i2c-0", O_RDWR);
  ioctl(i2c_rtc, I2C_SLAVE, addr);
}

void rtc_read(unsigned char *buf, int reg, int n)
{
  buf[0] = reg;
  write(i2c_rtc, buf, 1);
  read(i2c_rtc, buf, n);
}

void i2cdemo(void)
{
  int i;
  unsigned char buf[7];
  // mask for BCD          SEC   MIN   HOUR  WKDAY DAY   MONTH YEAR
  unsigned char mask[7] = {0x7F, 0x7F, 0x3F, 0x07, 0x3F, 0x1F, 0xFF};

  rtc_read(buf, 0, sizeof(buf));
  for(i = sizeof(buf)-1; i >= 0; i--)
    printf(" %02x", buf[i] & mask[i]);
  printf("\n");
}

int main(int argc, char *argv[])
{
  int i;
  rtc_open(0x6F);
  for(i = 0; i < 60; i++)
  {
    i2cdemo();
    sleep(1);
  }
  return 0;
}
root@buildroot:/home/root/rtc# ./a.out 
 20 09 22 02 21 14 27
 20 09 22 02 21 14 28
 20 09 22 02 21 14 29
 20 09 22 02 21 14 30
 20 09 22 02 21 14 31

saxonsoc jtag

https://gitter.im/ulx3s/Lobby?at=5f78c209dfe47e4d57464c10

Lawrie Griffiths @lawrie Oct 03 20:25

The pins to connect to are these - https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.1/hardware/synthesis/radiona/ulx3s/smp/ulx3s_v20_linux_uboot.lpf#L342-L348

emard @emard Oct 03 20:26

I tried to upload SVF file and it works, (fast). Yes, this pins connection is important. Is there a simple JTAG openocd scan command I can test it to make sure I connected all
Some command similar to

jtag newtap lfe5 tap -expected-id 0x21111043 -irlen 8 -irmask 0xFF -ircapture 0x5

Dolu1990 @Dolu1990 Oct 03 20:29

hoo when openocd run it scan everything

emard @emard Oct 03 20:29

yes yes I see it on above linked script

Dolu1990 @Dolu1990 Oct 03 20:30

i'm not sur there a command to rescan, just rerun it ^^

emard @emard Oct 03 20:31

OK I need to make a bit on the solder and pins to board, then I will test it and when I get vexrisc scanned by openocd jtag I will put it online for remote access

Dolu1990 @Dolu1990 Oct 03 20:31

you should get a scan like 0x10001FFF

Lawrie Griffiths @lawrie Oct 03 20:33

@Dolu1990 Doesn't @emard need to build your version of openocd - https://github.com/SpinalHDL/openocd_riscv

Dolu1990 @Dolu1990 Oct 03 20:34

Yes
so :
You can source the source.sh, and then do a saxon_clone; saxon_openocd
this will build it
Then modify https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.1/bsp/radiona/ulx3s/smp/openocd/usb_connect.cfg#L2 to match the jtag you have installed, and then saxon_openocd_connect

Dolu1990 @Dolu1990 Oct 03 21:02

sudo apt-get install libtool automake libusb-1.0.0-dev texinfo libusb-dev libyaml-dev pkg-config for the full depedency on debian

emard @emard 00:00

Escape character is '^]'.
Open On-Chip Debugger
> init 
> scan_chain
   TapName             Enabled  IdCode     Expected   IrLen IrCap IrMask
-- ------------------- -------- ---------- ---------- ----- ----- ------
 0 fpga_spinal.bridge     Y     0x10001fff 0x10001fff     4 0x01  0x0f

Got openocd to connect

https://gitter.im/ulx3s/Lobby?at=5f7c33646e0eb844696af0a2

Lawrie Griffiths @lawrie 11:05

You then need a usb JTAG device, preferably an FT2232 one, and you connect the pins to gn0 - gn3. I have not used openocd with SaxonSoc for a while, but @Dolu1990 uses it all the time.

micropython socks

https://gitter.im/ulx3s/Lobby/archives/2020/10/10?at=5f820bfb07361f0cc6430489

kost @kost Oct 10 19:31 UTC

since you guys around SaxonSoc made such a great progress. I had to do my part of the promise.
Just released socks server for micropython at https://github.com/kost/micropython-socks
that means you can tunnel any SOCKS5 connection over ESP32
since micropython does not come with NAT support, that means you can go to the internet over ESP32 using SOCKS server.
Installation is simple if you have connected ESP32 already to the internet:
You have to run this on ulx3s repl shell:

import upip
upip.install('micropython-socks')

and then you can just simply say:

import socks
socks.start()

it will start listening on 0.0.0.0:1080 for SOCKS5 connections.
Then you can simply from SaxonSoc test it with the following (or any other host):

curl --socks5 192.168.4.1:1080 http://ifconfig.co

nmigen - OV7670 with st7789

https://gitter.im/ulx3s/Lobby?at=5f949a4e6c8d484be2a6df34

Lawrie Griffiths @lawrie Oct 24 23:19

@goran-mahovlic I now have a version of the OV7670 camera application working in nmigen with the st7789 display - https://github.com/lawrie/ulx3s-nmigen-examples/tree/master/ov7670

oberon

https://gitter.im/ulx3s/Lobby?at=5f949d40270d004bcfea9716

Charles Perkins @charlesap Oct 24 23:31

@pnru_gitlab @emard I have created a new disk image based on the www.projectoberon.com sources, only adding some more LED output in the inner core boot process.

Here's a zip file of a disk image that you should be able to directly write to an SD card: https://github.com/io-core/io/blob/main/images/ledboot.img.zip ... this image has the Oberon partition at the correct offset but I did not bother to format the first part with a FAT partition. It boots on my ulx3s with the earlier Oberon .bit file.

Here's the meaning of the LEDs on booting:
LEDs: 7------- In BootLoad Firmware
LEDs: 7-----1- In BootLoad Firmware
LEDs: 7----2-- In BootLoad Firmware
LEDs: -------0 Control transferred to Modules
LEDs: ------1- Control transferred to Files
LEDs: -----2-- Control transferred to Kernel
LEDs: ----3--- In Kernel - Temporary Trap installed
LEDs: ---4---- In Kernel - Stack and heap origins and limits configured
LEDs: --5----- Kernel SecMap initialized, control transferred to FileDir
LEDs: -6------ Directory traversal complete
LEDs: 7------- Sectors marked, control transferred to Modules which has loaded Oberon.
LEDs: -------- Icons are defined, display subsystem initialized, ready to load System.
LEDs: --5----0 GC in the Oberon Loop
LEDs: --5---10 GC in the Oberon Loop
LEDs: --5--210 GC in the Oberon Loop
LEDs: --5-----

If there is an early trap before the system introduces a nicer printing trap the leds will fast-blink now with the trap value (0-7).
If the system gets an error trying to load modules after the boot loader successfully loads the kernel (which Oberon needs to actually display graphics and text to the screen) then this code fast-blinks bit zero.

The Oberon source code modified with the LED output is here:

https://github.com/io-orig/projectoberon/blob/main/Kernel.Mod.NL
https://github.com/io-orig/projectoberon/blob/main/FileDir.Mod.NL
https://github.com/io-orig/projectoberon/blob/main/Files.Mod.NL
https://github.com/io-orig/projectoberon/blob/main/Modules.Mod.NL
https://github.com/io-orig/projectoberon/blob/main/Oberon.Mod.NL

oled pins

https://gitter.im/ulx3s/Lobby?at=5fa2bcb374152347c213d4ae

emard @emard Nov 04 11:59

@sthornington yes bitstream projects do rearrange pins. At least GND and 3.3V must match, FPGA is flexible about pins, practical is to plug display directly without wires. Original markings are for SSD1331. ST7789 7-pin is similar but I think pin has BL (backlight) function instead of CS. wifi_gpio17 refers to the same thing and also ESP32 is flexible about SPI pinout so you can match practicaly any combination.
esp32 Channels 1 or 2 itself are the same but if you mount SD card from ESP32 it will always use channel 1 so channel 2 remains free. Without SD channel 1 or 2 are for display the same.

@sthornington of course GND and VCC can't be swapped by FPGA, because OLED draws current and must connect to hard power supply, can't be powered from FPGA 16mA pins (so low power devices actually could swap even GND/VCC). new board will have 8-pin LCD header instead of 7-pin but there's really crowded with routing so additional 2 pins are nearly impossible. But if display has GND and VCC swapped, then it will fit to external connector GN/GN 0-27 so there's still a possibility to plug such display directly on board on the side

rtc - i2c master example

https://gitter.im/ulx3s/Lobby?at=5fa7ba79c6fe0131d4e19d31

emard @emard Nov 08 10:29

There is example https://github.com/emard/ulx3s-misc/tree/master/examples/rtc/i2c_master/proj which makes i2c master in verilog, talks to RTC and displays time as HEX on DVI and LCD. There can't be interference with ESP32 because ESP32 is not directly connected to RTC, FPGA is between them.

rt2232 second channel openocd

https://gitter.im/ulx3s/Lobby?at=5fc57a82150b213e980592d8

emard @emard 00:04

@sthornington if you have external ft2232 it is fastest and normally used as openocd jtag debugger for softcore cpus like litex or saxonsoc linux. Secondary US1 channel is possible and fully supported by openocd, but it will be unacceptably slow to transfer big files like kernel or root fs images. https://github.com/emard/ulx3s-jtagthru/blob/master/scripts/ft231x2.ocd here is some project that has openocd script to export secondard jtag channel to external pins but normally you can use it internally to soft-core too. See also the schematics for your board (v3.0.8) how FTDI is connected to FPGA

Simon Thornington @sthornington 01:04

@emard thanks, mostly what I want to get going is an on-board scope to dump traces, is there any particular recommended F2232 interface? Does that plug into the jtag header of the below the oled one?

emard @emard 02:56

any FT2232 breakout board or programmer is ok. It should connect to external pins GP/GN something, depends on where litex/saxonsoc expects them, usually pins 0-5 I guess. I does not plug to JTAG header, it doesn't need to program ECP5 but the CPU RISC5 done by FPGA. If you need onboard scope to display traces in realtime check hdl4fpga project, it has great scope for our boards.

esp32 passthrough

https://gitter.im/ulx3s/Lobby?at=601c699dd0d32d7d4fc94dfc

liebman @liebman Feb 04 22:39

@emard this one is improved. It tristates gpio0 instead if setting it high so that it can be used elsewhere if needed. Also added an enable that can be used as a reset for the esp32.

module ulx3s_passthru (
  input  wire txd,
  output wire rxd,
  input  wire dtr,
  input  wire rts,
  input  wire esp_txd,
  output wire esp_rxd,
  output wire esp_en,
  output wire esp_io0,
  input  wire en,
);
  // TX/RX passthru
  assign rxd     = esp_txd;
  assign esp_rxd = txd;

  // Programming logic
  // SERIAL  ->  ESP32
  // DTR RTS -> EN IO0
  //  1   1     1   Z
  //  0   0     1   Z
  //  1   0     0   Z
  //  0   1     1   0
  assign esp_en  = (~dtr |  rts) & en;
  assign esp_io0 = ( dtr | ~rts) ? 1'bz : 1'b0; // we only want to drive this pin low

endmodule

can be called like

module top(
    input wire clk_25mhz,
    output wire ftdi_rxd,
    input wire ftdi_txd,
    inout wire ftdi_ndtr,
    inout wire ftdi_nrts,
    output wire wifi_rxd,
    input wire wifi_txd,
    inout wire wifi_en,
    inout wire wifi_gpio0,
    output [7:0] led,
    input  [6:0] btn,
    output wire shutdown,
);
    ulx3s_passthru passthru(.txd(ftdi_txd),
                            .rxd(ftdi_rxd),
                            .dtr(ftdi_ndtr),
                            .rts(ftdi_nrts),
                            .esp_txd(wifi_txd),
                            .esp_rxd(wifi_rxd),
                            .esp_en(wifi_en),
                            .esp_io0(wifi_gpio0),
                            .en(btn[0]),  // btn[0] will work as a reset for esp
    );

    // blinky for something to do so we know its operational
    assign led[0]   = btn[1];
    assign led[6:1] = 0;
    assign led[7]   = wifi_gpio0;
endmodule

liebman @liebman Feb 04 23:18

thats good to know, which are the (non esp) pins that are clock capable?
(that explains why some of my tests failed)

emard @emard Feb 04 23:19

They are mentioned on pdf schematics_v3.0.8 let me see
https://github.com/emard/ulx3s/blob/master/doc/schematics_v308.pdf page 2 GP,GN 12 are clock capable and shared with ESP32 but small design fail is those pins are on ESP32 input only. In new board v3.1.5 I tried to fix this by routing one esp32 output capable pin to FPGA clock input capable...

PCLK .. means primary clock capable pins. they are best. GR_PCLK are second best, general routed to primary clock capable

A small fix could be possible with a jumper GN11-GN12 this will connect ESP32 pin 25 GN11 which is output capable to FPGA clock input capable at GN12

lpf documentation

https://gitter.im/ulx3s/Lobby?at=601fa45432e01b4f717e0ebb

Dave Anderson @danderson 09:27

Couldn't find any decent docs other than nextpnr source code and poorly explained technical notes from lattice, so I wrote https://github.com/danderson/ulxs/blob/main/lpf.md
Also comes with pointers to the Lattice tech notes that go into more detail about e.g. ECP5 configuration and I/O pin config.

hdmi

https://gitter.im/ulx3s/Lobby?at=6029a8349337c51bc688733e

splinedrive @splinedrive Feb 14 23:46

Hi, I have done a hdmi reimplementation for ulx3s and blackicemx (ice40) they have the same code base. I hope you like it. I learned from other projects to take the semantic (ulx3s-examples-dvi, fpga4fun, ...) . ulx3s has DDR and SRD support and blackicemx can only DDR. I used the pmod from Luke Wren. It works only with passive resistors and works with long hdmi cables without any problems. https://github.com/splinedrive/my_hdmi_device

osd

https://gitter.im/ulx3s/Lobby?at=603a1016457d6b4a948f3208

Lawrie Griffiths @lawrie 10:25

@sylefeb I am not sure that between us, @emard and I, have documented the OSD and rom loader very well. There are lots of versions of the code in different projects. This is the spi slave from my Z80 template project - https://github.com/lawrie/ulx3s_z80_template/blob/main/src/osd/spirw_slave_v.v
The rest of the code is in that osd directory.
This is a version of the micropython code that reads and writes memory and controls the cpu remotely from the esp32 - https://github.com/lawrie/ulx3s_z80_template/blob/main/esp32/spiram.py
The rest of the esp32 code including osd.py is in that directory.
Here is a youtube video that shows the osd and loader being used - https://www.youtube.com/watch?v=YE7pSuZiN9Y&t=8s
The latest version of the osd look a bit nicer.

This is my TRS 80 Model 1 implementation that has a short description on using the OSD - https://github.com/lawrie/ulx3s_z80_trs80
Perhaps @emard knows of a better description of all this.

The OSD and loader is used by many Ulx3s projects including the Apple II, C64, ZX Spectrum, Mac Plus, QL, TI-99/4A, Amiga (OSD only), Vic 20, NES, SNES, Sega Master System, Orao, etc.
This is a good video by @Speccery that shows the OSD used on the TI-99/4A - https://www.youtube.com/watch?v=zdST3wz00KU
I don't think there is a Risc-V implementation on the Ulx3s that uses the OSD yet.

emard @emard 12:16

@sylefeb @lawrie OSD loader behaves similar as SPI RAM using 32-bit byte address. FPGA behaves as SPI slave, ESP32 as SPI master. If slave needs to initiate transfer, there is additional IRQ line. Resources at SPI address space are memory mapped, RAM to upload for CPU, reset/halt control, buttons, OSD video chars, floppy disks etc. All is very simple and protocol is not too much standardized so it can be adapted to completely unusual usage. Generally for apple2 c64 vic20 mac trs80 etc we just copy-paste the same thing

saxonsoc memory map

https://gitter.im/ulx3s/Lobby?at=606dcc72bc8e6f2e0d2e5be9

Dolu1990 @Dolu1990 Apr 07 17:14

@irvise:matrix.org

    0x340000

That's the flash address. the CPU copy that part of the flash to the SDRAM at 0x80F80000 (global address). See :

    Memory copy : https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.3/bsp/radiona/ulx3s/smp/app/bootloaderConfig.h#L99
    source address : OPENSBI_FLASH
    destination address : OPENSBI_MEMORY

Then it does similar things with uboot but with that set of addresses : https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.3/bsp/radiona/ulx3s/smp/app/bootloaderConfig.h#L22

    if I generate a program that load to the address 0x380000 it should "just work"

Yes, as long you programe is complied to sit at 0x80F00000 in the global memory space

    And where can I find more info on what memory addresses are being used for MMIO

This autogenerated header file contains all the peripheral addresses :

https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.3/bsp/radiona/ulx3s/smp/include/soc.h#L64

    blink

See https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.3/software/standalone/blinkAndEcho/src/main.c
used with https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.3/bsp/radiona/ulx3s/smp/include/bsp.h#L15

you can compile it using the command "saxon_standalone_compile blinkAndEcho" It will sit where uboot sit (see https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.3/bsp/radiona/ulx3s/smp/linker/default.ld#L1)

nmigen

https://gitter.im/ulx3s/Lobby?at=608e7b59d5e2793379e961a8

Lawrie Griffiths @lawrie May 02 12:13

I am currently working on my nmigen OV7670 camera application - https://github.com/lawrie/ulx3s-nmigen-examples/blob/master/image/camtest.py
That now displays the image on the HDMI monitor and I am starting to add image signal processing functions like brightness and color control, and simple edge detection.

The latest code that I have pushed calculates the mouse pointer (p_x, p_y) - https://github.com/lawrie/ulx3s-nmigen-examples/blob/master/image/image_stream.py

If you set the ImageStream filter switch then pixels with a red channel value less than some threshold are filtered out and the remaining pixels are displayed on the HDMI monitor as pure red. You can adjust the threshold with the up and down arrows, and a value of about 30 seems best. As the threshold is increased the picture turns black except where the laser pointer points, and the spot gets smaller as the threshold is increased. I then calculate the min and max x and y values for those red pixels, and calculate the mid points as p_x and p_y. It seems to be working.

saxon esp32ecp5 start

https://gitter.im/ulx3s/Lobby?at=60b93a55a10461235db71cff

emard @emard Jun 03 22:23

I have just checked saxonsoc linux and it still works, lAN8720 ethernet (ssh) works out of the box. Tetris still compiles and works. A small hint here is the esp32 script for new esp32ecp5 to start linux

import os
from machine import SDCard, Pin
import ecp5

os.mount(SDCard(slot=3),"/sd")
# copy to root of SD card: dtb, rootfs.cpio.uboot, uImage
# flash with "False" without starting the bitstream
ecp5.flash("/sd/linux/smp/fw_jump.bin@0x340000",0x340000,False)
ecp5.flash("/sd/linux/smp/u-boot.bin@0x380000",0x380000,False)
ecp5.prog("/sd/linux/smp/ulx3s_12f_1core_saxonsoc.bit")
os.umount("/sd")
p12=Pin(12,Pin.IN)
p13=Pin(13,Pin.IN)
p14=Pin(14,Pin.IN)
p15=Pin(15,Pin.IN)

With esp32ecp5 I'd recommend micropython builds with idf3 because idf4 builds reboot ad SD card deinit (ftp> site umount)

permalink
Lamobo R1
GPIO 2.png

Lamobo/BananaPi R1

http://linux-sunxi.org/Lamobo_R1

Contents: [Dobrica Pavlinušić's random unstructured stuff]


upgrade to unsupported armbian

This board was last supported on jessie, but it's fully supported in upstream so I did upgrade to latest Armbian as of 2021-05-29.

u-boot

sdcard already had u-boot installed, so I didn't have to touch this in first step. To update
u-boot do following:

root@r1:/home/dpavlin# apt install u-boot-sunxi

root@r1:/home/dpavlin# dd conv=fsync,notrunc if=/usr/lib/u-boot/Lamobo_R1/u-boot-sunxi-with-spl.bin of=/dev/mmcblk0 bs=1024 seek=8
449+1 records in
449+1 records out
460103 bytes (460 kB, 449 KiB) copied, 0.0449233 s, 10.2 MB/s

distribution

First, I did distribution update to stretch and buster and than added

root@r1:/home/dpavlin# cat /etc/apt/sources.list.d/armbian.list
deb http://beta.armbian.com buster main

kernel

and installed latest sunxi kernel image

apt install linux-image-edge-sunxi

After reboot I was greeted with new kernel

root@r1:/home/dpavlin# uname -a
Linux r1 5.12.7-sunxi #trunk.33 SMP Fri May 28 07:03:36 UTC 2021 armv7l GNU/Linux

configure switch

https://www.kernel.org/doc/html/latest/networking/dsa/b53.html

root@r1:/home/dpavlin# cat /etc/network/interfaces.d/br0
auto br0
iface br0 inet dhcp
#iface br0 inet manual
#	address 192.168.1.1
#	netmask 255.255.255.0
	bridge_ports eth0 wan lan1 lan2 lan3 lan4
	post-up for i in `seq 0 4`; do ip link set up dev lan${i}; done ; ip link set up dev wlan
	bridge_stp off
        bridge_waitport 0
	bridge_fd 0

Ports are (left-to-right, looking from back of board starting at edge towards hdmi connector):

br0: port 3(lan1) entered disabled state
br0: port 4(lan2) entered blocking state
br0: port 4(lan2) entered forwarding state
br0: port 4(lan2) entered disabled state
br0: port 5(lan3) entered blocking state
br0: port 5(lan3) entered forwarding state
br0: port 5(lan3) entered disabled state
br0: port 6(lan4) entered blocking state
br0: port 6(lan4) entered forwarding state
br0: port 6(lan4) entered disabled state
br0: port 2(wan) entered blocking state
br0: port 2(wan) entered forwarding state

switch connects all ports on boot

https://github.com/armbian/build/issues/511#issuecomment-258647387

DSA config on armbian for r1

uart

Connect your UART adapter here:

UART0-RX: J13-P01
UART0-TX: J13-P02
GND: J12-P08

                          GND TX RX
             J12   o  o  o  o  o  o
{SD slot}          o  o  o  o


switch

https://www.mail-archive.com/netdev@vger.kernel.org/msg150526.html

port mirroring

https://www.mail-archive.com/netdev@vger.kernel.org/msg150526.html

# ingress
      tc qdisc  add dev eth1 handle ffff: ingress
      tc filter add dev eth1 parent ffff:           \
               matchall skip_sw                      \
               action mirred egress mirror           \
               dev eth2
# egress
      tc qdisc add dev eth1 handle 1: root prio
      tc filter add dev eth1 parent 1:               \
               matchall skip_sw                       \
               action mirred egress mirror            \
               dev eth2

usb otg

http://git.rot13.org/?p=usb-otg;a=summary

usbproxy

make sure that there are no other usb modules loaded (libcomposite or g_*)

mitm usb otg machine

dpavlin@r1:~/USBProxy$ git remote -v
origin  https://github.com/dominicgs/USBProxy (fetch)
origin  https://github.com/dominicgs/USBProxy (push)

dpavlin@r1:~/USBProxy/src/build$ sudo usb-mitm -l -v 058f -p 6387 -P PacketFilter_MassStorage
Loading plugins from /usr/local/lib/USBProxy/
vendorId=058f
productId=6387
cleaning up /tmp
removing 1
Made directory /tmp/gadget-SOOBVj for gadget
UnblockPassword=
Printing Config data
        Strings: 4
                DeviceProxy: DeviceProxy_LibUSB
                HostProxy: HostProxy_GadgetFS
                productId: 6387
                vendorId: 058f
        Vectors: 1
                Plugins:
                        PacketFilter_StreamLog
                        PacketFilter_MassStorage
Pointer: 1
                PacketFilter_StreamLog::file: 0xb6d779f0
Device: 12 01 00 02 00 00 00 40 8f 05 87 63 00 01 01 02 03 01
  Manufacturer: JetFlash
  Product:      Mass Storage Device
  Serial:       GUYOBHDU
        *Config(1): 09 02 20 00 01 01 00 80 32
                Interface(0):
                        *Alt(0): 09 04 00 00 02 08 06 50 00
                                EP(01): 07 05 01 02 00 02 00
                                EP(82): 07 05 82 02 00 02 00
HS Qualifier: 0a 06 00 02 00 00 00 40 01 00
         Config(1): 09 07 20 00 01 01 00 80 32
                Interface(0):
                        *Alt(0): 09 04 00 00 02 08 06 50 00
                                EP(01): 07 05 01 02 40 00 00
                                EP(82): 07 05 82 02 40 00 00
searching in [/tmp/gadget-SOOBVj]
Starting injector thread (14796) for [Injector].
Injector In FD[1/1]: 3
Starting setup writer thread (14799) for EP00.
Starting setup reader thread (14797) for EP00.
[80 06 00 03 00 00 ff 00]
[80 06 00 03 00 00 04 00]: 04 03 09 04
[80 06 02 03 09 04 ff 00]
[80 06 02 03 09 04 28 00]:
        28 03 4d 00 61 00 73 00 73 00 20 00 53 00 74 00 6f 00 72 00 61 00 67 00 65 00 20 00 44 00 65 00
        76 00 69 00 63 00 65 00
[80 06 01 03 09 04 ff 00]
[80 06 01 03 09 04 12 00]: 12 03 4a 00 65 00 74 00 46 00 6c 00 61 00 73 00 68 00
[80 06 03 03 09 04 ff 00]
[80 06 03 03 09 04 12 00]: 12 03 47 00 55 00 59 00 4f 00 42 00 48 00 44 00 55 00
[00 09 01 00 00 00 00 00]
Opened EP01
Opened EP82
Starting writer thread (14802) for EP01.
Starting reader thread (14803) for EP82.
Starting writer thread (14804) for EP82.
Starting reader thread (14801) for EP01.
[a1 fe 00 00 00 00 01 00]
[a1 fe 00 00 00 00 00 00]
01[31]: 55 53 42 43 01 00 00 00 24 00 00 00 80 00 06 12 00 00 00 24 00 00 00 00 00 00 00 00 00 00 00
CBW: (12), tag: 01 00 00 00

[80 06 03 03 09 04 ff 00]
[80 06 03 03 09 04 12 00]: 12 03 47 00 55 00 59 00 4f 00 42 00 48 00 44 00 55 00
[00 09 01 00 00 00 00 00]


original target device

dpavlin@nuc:~$ journalctl -t kernel -f
Sep 01 11:10:04 nuc kernel: usb 2-4.4.2: new high-speed USB device number 45 using xhci_hcd
Sep 01 11:10:04 nuc kernel: usb 2-4.4.2: New USB device found, idVendor=058f, idProduct=6387
Sep 01 11:10:04 nuc kernel: usb 2-4.4.2: New USB device strings: Mfr=1, Product=2, SerialNumber=3
Sep 01 11:10:04 nuc kernel: usb 2-4.4.2: Product: Mass Storage Device
Sep 01 11:10:04 nuc kernel: usb 2-4.4.2: Manufacturer: JetFlash
Sep 01 11:10:04 nuc kernel: usb 2-4.4.2: SerialNumber: GUYOBHDU
Sep 01 11:10:04 nuc kernel: usb-storage 2-4.4.2:1.0: USB Mass Storage device detected
Sep 01 11:10:04 nuc kernel: scsi host5: usb-storage 2-4.4.2:1.0

# BUT!

dpavlin@nuc:~$ sudo fdisk -l /dev/sdb
fdisk: cannot open /dev/sdb: No medium found


WiringPi

dpavlin@r1:~/BPI-WiringPi2$ git remote -v
lanefu  https://github.com/lanefu/WiringOtherPi (fetch)
lanefu  https://github.com/lanefu/WiringOtherPi (push)
origin  https://github.com/BPI-SINOVOIP/BPI-WiringPi2 (fetch)
origin  https://github.com/BPI-SINOVOIP/BPI-WiringPi2 (push)

dpavlin@r1:~/BPI-WiringPi2$ gpio readall
 +-----+-----+----------+------+---+-Orange Pi+---+---+------+---------+-----+--+
 | BCM | wPi |   Name   | Mode | V | Physical | V | Mode | Name     | wPi | BCM |
 +-----+-----+----------+------+---+----++----+---+------+----------+-----+-----+
 |     |     |     3.3v |      |   |  1 || 2  |   |      | 5v       |     |     |
 |  12 |   8 |    SDA.0 |   IN | 0 |  3 || 4  |   |      | 5V       |     |     |
 |  11 |   9 |    SCL.0 |   IN | 0 |  5 || 6  |   |      | 0v       |     |     |
 |   6 |   7 |   GPIO.7 |   IN | 0 |  7 || 8  | 0 | IN   | TxD3     | 15  | 13  |
 |     |     |       0v |      |   |  9 || 10 | 0 | IN   | RxD3     | 16  | 14  |
 |   1 |   0 |     RxD2 |   IN | 0 | 11 || 12 | 0 | IN   | GPIO.1   | 1   | 110 |
 |   0 |   2 |     TxD2 |   IN | 0 | 13 || 14 |   |      | 0v       |     |     |
 |   3 |   3 |     CTS2 |   IN | 0 | 15 || 16 | 0 | IN   | GPIO.4   | 4   | 68  |
 |     |     |     3.3v |      |   | 17 || 18 | 0 | IN   | GPIO.5   | 5   | 71  |
 |  64 |  12 |     MOSI |   IN | 0 | 19 || 20 |   |      | 0v       |     |     |
 |  65 |  13 |     MISO |   IN | 0 | 21 || 22 | 0 | IN   | RTS2     | 6   | 2   |
 |  66 |  14 |     SCLK |   IN | 0 | 23 || 24 | 0 | IN   | CE0      | 10  | 67  |
 |     |     |       0v |      |   | 25 || 26 | 0 | IN   | GPIO.11  | 11  | 21  |
 |  19 |  30 |    SDA.1 |   IN | 0 | 27 || 28 | 0 | IN   | SCL.1    | 31  | 18  |
 |   7 |  21 |  GPIO.21 |   IN | 0 | 29 || 30 |   |      | 0v       |     |     |
 |   8 |  22 |  GPIO.22 |   IN | 0 | 31 || 32 | 0 | IN   | RTS1     | 26  | 200 |
 |   9 |  23 |  GPIO.23 |   IN | 0 | 33 || 34 |   |      | 0v       |     |     |
 |  10 |  24 |  GPIO.24 |   IN | 0 | 35 || 36 | 0 | IN   | CTS1     | 27  | 201 |
 |  20 |  25 |  GPIO.25 |   IN | 0 | 37 || 38 | 0 | IN   | TxD1     | 28  | 198 |
 |     |     |       0v |      |   | 39 || 40 | 0 | IN   | RxD1     | 29  | 199 |
 +-----+-----+----------+------+---+----++----+---+------+----------+-----+-----+
 | BCM | wPi |   Name   | Mode | V | Physical | V | Mode | Name     | wPi | BCM |
 +-----+-----+----------+------+---+-Orange Pi+---+------+----------+-----+-----+



TMP75

root@r1:/etc/telegraf# i2cdetect -y 1
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f
00:          -- -- -- -- -- -- -- -- -- -- -- -- -- 
10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 
20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 
30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 
40: -- -- -- -- -- -- -- -- -- 49 -- -- -- -- -- -- 
50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 
60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 
70: -- -- -- -- -- -- -- --                         


userland

dpavlin@r1:~$ cc tmp.c -o tmp -lm
dpavlin@r1:~$ sudo ./tmp /dev/i2c-1 0x49
21.5


kernel hwmomn lm75 driver

root@r1:~# echo lm75 0x49 > /sys/bus/i2c/devices/i2c-1/new_device 

root@r1:~# dmesg | tail -2
[68352.599623] lm75 1-0049: hwmon1: sensor 'lm75'
[68352.599719] i2c i2c-1: new_device: Instantiated device lm75 at 0x49

root@r1:/sys/bus/i2c/devices/i2c-1# sensors
sun4i_ts-isa-0000
Adapter: ISA adapter
SoC temperature:  +44.4°C  

lm75-i2c-1-49
Adapter: mv64xxx_i2c adapter
temp1:        +22.0°C  (high = +80.0°C, hyst = +75.0°C)

network performance

kernel 3.4

root@r1:~# uname -a
Linux r1 3.4.113-sun7i #23 SMP PREEMPT Wed Jun 14 23:57:45 CEST 2017 armv7l GNU/Linux

root@r1:~# iperf3 --reverse --client nuc
Connecting to host nuc, port 5201
Reverse mode, remote host nuc is sending
[  4] local 192.168.3.238 port 58203 connected to 192.168.3.40 port 5201
[ ID] Interval           Transfer     Bandwidth
[  4]   0.00-1.00   sec   107 MBytes   897 Mbits/sec                  
[  4]   1.00-2.00   sec   110 MBytes   923 Mbits/sec                  
[  4]   2.00-3.00   sec   111 MBytes   935 Mbits/sec                  
[  4]   3.00-4.00   sec   107 MBytes   894 Mbits/sec                  
[  4]   4.00-5.00   sec   111 MBytes   927 Mbits/sec                  
[  4]   5.00-6.00   sec   110 MBytes   922 Mbits/sec                  
[  4]   6.00-7.00   sec   111 MBytes   928 Mbits/sec                  
[  4]   7.00-8.00   sec   111 MBytes   935 Mbits/sec                  
[  4]   8.00-9.00   sec   111 MBytes   928 Mbits/sec                  
[  4]   9.00-10.00  sec   111 MBytes   931 Mbits/sec                  
- - - - - - - - - - - - - - - - - - - - - - - - -
[ ID] Interval           Transfer     Bandwidth       Retr
[  4]   0.00-10.00  sec  1.08 GBytes   924 Mbits/sec  147             sender
[  4]   0.00-10.00  sec  1.07 GBytes   922 Mbits/sec                  receiver

iperf Done.

root@r1:~# iperf3 --client nuc
Connecting to host nuc, port 5201
[  4] local 192.168.3.238 port 58205 connected to 192.168.3.40 port 5201
[ ID] Interval           Transfer     Bandwidth       Retr  Cwnd
[  4]   0.00-1.00   sec  51.3 MBytes   428 Mbits/sec    0    239 KBytes       
[  4]   1.00-2.01   sec  52.5 MBytes   436 Mbits/sec    0    240 KBytes       
[  4]   2.01-3.02   sec  52.5 MBytes   436 Mbits/sec    0    245 KBytes       
[  4]   3.02-4.01   sec  50.0 MBytes   424 Mbits/sec    0    246 KBytes       
[  4]   4.01-5.02   sec  51.2 MBytes   429 Mbits/sec    0    247 KBytes       
[  4]   5.02-6.02   sec  52.5 MBytes   439 Mbits/sec    0    250 KBytes       
[  4]   6.02-7.03   sec  51.2 MBytes   427 Mbits/sec    0    253 KBytes       
[  4]   7.03-8.00   sec  48.8 MBytes   418 Mbits/sec    0    256 KBytes       
[  4]   8.00-9.02   sec  52.5 MBytes   432 Mbits/sec    0    256 KBytes       
[  4]   9.02-10.01  sec  51.2 MBytes   435 Mbits/sec    0    256 KBytes       
- - - - - - - - - - - - - - - - - - - - - - - - -
[ ID] Interval           Transfer     Bandwidth       Retr
[  4]   0.00-10.01  sec   514 MBytes   431 Mbits/sec    0             sender
[  4]   0.00-10.01  sec   514 MBytes   431 Mbits/sec                  receiver

kernel 4.13

root@r1:~# uname -a
Linux r1 4.13.10-sunxi #57 SMP Mon Oct 30 00:08:27 CET 2017 armv7l GNU/Linux

root@r1:~# iperf3 --client nuc
Connecting to host nuc, port 5201
[  4] local 192.168.3.238 port 59520 connected to 192.168.3.40 port 5201
[ ID] Interval           Transfer     Bandwidth       Retr  Cwnd
[  4]   0.00-1.00   sec  67.9 MBytes   567 Mbits/sec    0    765 KBytes       
[  4]   1.00-2.01   sec  82.1 MBytes   687 Mbits/sec    0    840 KBytes       
[  4]   2.01-3.01   sec  65.7 MBytes   547 Mbits/sec    0   1.13 MBytes       
[  4]   3.01-4.02   sec  80.0 MBytes   669 Mbits/sec    0   1.13 MBytes       
[  4]   4.02-5.00   sec  76.2 MBytes   648 Mbits/sec    0   1.24 MBytes       
[  4]   5.00-6.00   sec  81.2 MBytes   681 Mbits/sec    0   1.24 MBytes       
[  4]   6.00-7.06   sec  82.5 MBytes   656 Mbits/sec    0   1.33 MBytes       
[  4]   7.06-8.00   sec  80.0 MBytes   712 Mbits/sec    0   1.33 MBytes       
[  4]   8.00-9.00   sec  78.8 MBytes   659 Mbits/sec    0   1.61 MBytes       
[  4]   9.00-10.00  sec  83.8 MBytes   702 Mbits/sec    0   2.08 MBytes       
- - - - - - - - - - - - - - - - - - - - - - - - -
[ ID] Interval           Transfer     Bandwidth       Retr
[  4]   0.00-10.00  sec   778 MBytes   653 Mbits/sec    0             sender
[  4]   0.00-10.00  sec   775 MBytes   650 Mbits/sec                  receiver

iperf Done.

root@r1:~# iperf3 --reverse --client nuc
Connecting to host nuc, port 5201
Reverse mode, remote host nuc is sending
[  4] local 192.168.3.238 port 59524 connected to 192.168.3.40 port 5201
[ ID] Interval           Transfer     Bandwidth
[  4]   0.00-1.00   sec  98.0 MBytes   822 Mbits/sec                  
[  4]   1.00-2.00   sec   112 MBytes   933 Mbits/sec                  
[  4]   2.00-3.00   sec   107 MBytes   904 Mbits/sec                  
[  4]   3.00-4.00   sec   107 MBytes   898 Mbits/sec                  
[  4]   4.00-5.00   sec   108 MBytes   904 Mbits/sec                  
[  4]   5.00-6.00   sec   108 MBytes   903 Mbits/sec                  
[  4]   6.00-7.00   sec   108 MBytes   904 Mbits/sec                  
[  4]   7.00-8.00   sec   108 MBytes   904 Mbits/sec                  
[  4]   8.00-9.00   sec   108 MBytes   904 Mbits/sec                  
[  4]   9.00-10.00  sec   107 MBytes   899 Mbits/sec                  
- - - - - - - - - - - - - - - - - - - - - - - - -
[ ID] Interval           Transfer     Bandwidth       Retr
[  4]   0.00-10.00  sec  1.05 GBytes   900 Mbits/sec   69             sender
[  4]   0.00-10.00  sec  1.05 GBytes   898 Mbits/sec                  receiver



kernel 5.12.7

dpavlin@r1:~$ uname -a
Linux r1 5.12.7-sunxi #trunk.33 SMP Fri May 28 07:03:36 UTC 2021 armv7l GNU/Linux

dpavlin@r1:~$ iperf3 -c nuc
Connecting to host nuc, port 5201
[  5] local 192.168.3.238 port 50136 connected to 192.168.3.40 port 5201
[ ID] Interval           Transfer     Bitrate         Retr  Cwnd
[  5]   0.00-1.02   sec  41.9 MBytes   346 Mbits/sec    0    239 KBytes
[  5]   1.02-2.02   sec  53.8 MBytes   448 Mbits/sec    0    266 KBytes
[  5]   2.02-3.00   sec  42.5 MBytes   363 Mbits/sec    0    266 KBytes
[  5]   3.00-4.02   sec  53.8 MBytes   445 Mbits/sec    0    277 KBytes
[  5]   4.02-5.01   sec  53.8 MBytes   456 Mbits/sec    0    325 KBytes
[  5]   5.01-6.02   sec  48.1 MBytes   400 Mbits/sec    0    386 KBytes
[  5]   6.02-7.03   sec  48.8 MBytes   405 Mbits/sec    0    386 KBytes
[  5]   7.03-8.00   sec  46.2 MBytes   397 Mbits/sec    0    386 KBytes
[  5]   8.00-9.02   sec  53.8 MBytes   443 Mbits/sec    0    393 KBytes
[  5]   9.02-10.00  sec  51.2 MBytes   438 Mbits/sec    0    393 KBytes
- - - - - - - - - - - - - - - - - - - - - - - - -
[ ID] Interval           Transfer     Bitrate         Retr
[  5]   0.00-10.00  sec   494 MBytes   414 Mbits/sec    0             sender
[  5]   0.00-10.01  sec   494 MBytes   414 Mbits/sec                  receiver

iperf Done.
dpavlin@r1:~$ iperf3 -R -c nuc
Connecting to host nuc, port 5201
Reverse mode, remote host nuc is sending
[  5] local 192.168.3.238 port 50140 connected to 192.168.3.40 port 5201
[ ID] Interval           Transfer     Bitrate
[  5]   0.00-1.01   sec  66.9 MBytes   559 Mbits/sec
[  5]   1.01-2.00   sec  69.8 MBytes   588 Mbits/sec
[  5]   2.00-3.00   sec  66.8 MBytes   560 Mbits/sec
[  5]   3.00-4.00   sec  67.6 MBytes   567 Mbits/sec
[  5]   4.00-5.00   sec  67.6 MBytes   568 Mbits/sec
[  5]   5.00-6.00   sec  65.3 MBytes   548 Mbits/sec
[  5]   6.00-7.00   sec  66.5 MBytes   558 Mbits/sec
[  5]   7.00-8.00   sec  65.4 MBytes   549 Mbits/sec
[  5]   8.00-9.00   sec  66.7 MBytes   560 Mbits/sec
[  5]   9.00-10.00  sec  65.2 MBytes   547 Mbits/sec
- - - - - - - - - - - - - - - - - - - - - - - - -
[ ID] Interval           Transfer     Bitrate         Retr
[  5]   0.00-10.01  sec   672 MBytes   563 Mbits/sec   57             sender
[  5]   0.00-10.00  sec   668 MBytes   560 Mbits/sec                  receiver

iperf Done.
permalink
Turris Omnia


documentation

reset modes

https://www.turris.cz/doc/en/howto/omnia_factory_reset

 Available reset modes:

    1 LED: Standard (re)boot
    2 LEDs: Rollback to latest snapshot
    3 LEDs: Rollback to factory reset
    4 LEDs: Re-flash router from flash drive
    5 LEDs or more: Boot to rescue shell

vlan

GPIO pinout

omnia-pin-header.png

PWM same on all pins

Debian

root@turris:/mnt/tmp# wget http://aule.elfove.cz/~brill/omnia-debian/omnia-medkit-20170330.tar.gz

# boot into rescue mode

root@(none):~# mount /dev/mmcblk0p1 /target/

root@(none):~# btrfs subvolume create /target/@debian


watchdog will timeout, but you will eventually have subvolume visible from u-boot (which is not case if you just create subvolume from Turris OS

root@turris:/# btrfs sub create @debian
Create subvolume './@debian'

root@turris:/# cd /@debian
root@turris:/@debian# tar xf /mnt/tmp/omnia-medkit-20170330.tar.gz 
root@turris:/@debian# btrfs fi df .
System, single: total=32.00MiB, used=4.00KiB
Data+Metadata, single: total=3.68GiB, used=2.25GiB
GlobalReserve, single: total=48.00MiB, used=0.00B

root@turris:/@debian# vi etc/network/interfaces
auto br0
iface br0 inet static
        bridge_ports wlan0 eth0 eth2
        address 192.168.3.254
        netmask 255.255.255.0
        gateway 192.168.3.1
root@turris:~# echo b > /proc/sysrq-trigger
[54760.278340] sysrq: SysRq : Resetting
[54760.282039] CPU1: stopping
   
U-Boot SPL 2015.10-rc2 (Aug 18 2016 - 20:43:35)
High speed PHY - Version: 2.0
SERDES0 card detect: NONE
   
Initialize Turris board topology
Detected Device ID 6820
board SerDes lanes topology details:
 | Lane #  | Speed |  Type       |
 --------------------------------
 |   0    |  5   |  PCIe0       |
 |   1    |  5   |  USB3 HOST0  |
 |   2    |  5   |  PCIe1       |
 |   3    |  5   |  USB3 HOST1  |
 |   4    |  5   |  PCIe2       |
 |   5    |  0   |  SGMII2      |
 --------------------------------
poll_op_execute: TIMEOUT
PCIe, Idx 0: detected no link
PCIe, Idx 1: detected no link
PCIe, Idx 2: detected no link
High speed PHY - Ended Successfully
DDR3 Training Sequence - Ver TIP-1.29.0
Memory config in EEPROM: 0x01
DDR3 Training Sequence - Switching XBAR Window to FastPath Window
DDR3 Training Sequence - Ended Successfully

   
U-Boot 2015.10-rc2 (Aug 18 2016 - 20:43:35 +0200), Build: jenkins-omnia-master-23
   
SoC:   MV88F6820-A0
       Watchdog enabled
I2C:   ready
SPI:   ready
DRAM:  1 GiB (ECC not enabled)
Enabling Armada 385 watchdog.
Disabling MCU startup watchdog.
Regdomain set to **
MMC:   mv_sdh: 0
SF: Detected S25FL164K with page size 256 Bytes, erase size 64 KiB, total 8 MiB
*** Warning - bad CRC, using default environment
   
Model: Marvell Armada 385 GP
Board: Turris Omnia SN: 0000000B0000B8E5
Regdomain set to **
SCSI:  MVEBU SATA INIT
SATA link 0 timeout.
SATA link 1 timeout.
AHCI 0001.0000 32 slots 2 ports 6 Gbps 0x3 impl SATA mode
flags: 64bit ncq led only pmp fbss pio slum part sxs
Net:   neta2
Hit any key to stop autoboot:  0
=> 

=> setenv debbootargs earlyprintk console=ttyS0,115200 rootfstype=btrfs rootwait root=/dev/mmcblk0p1 rootflags=subvol=@debian,commit=5 rw
=> setenv debboot 'setenv bootargs "$debbootargs cfg80211.freg=$regdomain"; btrload mmc 0 0x01000000 boot/vmlinuz @debian; btrload mmc 0 0x02000000 boot/dtb @debian; btrload mmc 0 0x03000000 boot/initrd.img @debian; bootz 0x01000000 0x03000000:$filesize 0x02000000'
=> saveenv
Saving Environment to SPI Flash...
SF: Detected S25FL164K with page size 256 Bytes, erase size 64 KiB, total 8 MiB
Erasing SPI flash...Writing to SPI flash...done

=> setenv defbootcmd "$bootcmd"
=> setenv debbootcmd 'i2c dev 1; i2c read 0x2a 0x9 1 0x00FFFFF0; setexpr.b rescue *0x00FFFFF0; if test $rescue -ge 2; then echo BOOT RESCUE; run rescueboot; else if test $rescue -ge 1; then echo BOOT eMMC TurrisOS FS; run mmcboot; else echo BOOT eMMC Debian FS; run debboot; fi; fi'
=> setenv bootcmd "$debbootcmd"
=> saveenv
Saving Environment to SPI Flash...
Erasing SPI flash...Writing to SPI flash...done

u-boot problem

Kernel image @ 0x1000000 [ 0x000000 - 0x332588 ]
Wrong Ramdisk Image Format
Ramdisk image is corrupt or invalid

https://docs.turris.cz/hw/omnia/serial-boot/#u-boot

update u-boot

=> dhcp
neta2:1 is connected to neta2.  Reconnecting to neta2
neta2 Waiting for PHY auto negotiation to complete............ done
BOOTP broadcast 1
BOOTP broadcast 2
BOOTP broadcast 3
BOOTP broadcast 4
BOOTP broadcast 5
*** Unhandled DHCP Option in OFFER/ACK: 208
*** Unhandled DHCP Option in OFFER/ACK: 208
DHCP client bound to address 192.168.4.113 (5583 ms)
*** Warning: no boot file name; using 'C0A80471.img'
Using neta2 device
TFTP from server 192.168.4.1; our IP address is 192.168.4.113
Filename 'C0A80471.img'.
Load address: 0x800000
Loading: *
TFTP error: 'file /var/tftp/C0A80471.img not found' (1)
Not retrying...
=> tftpboot 0x1000000 uboot-turris-omnia-spl.kwb
Using neta2 device
TFTP from server 192.168.4.1; our IP address is 192.168.4.113
Filename 'uboot-turris-omnia-spl.kwb'.
Load address: 0x1000000
Loading: #####################################
         2.6 MiB/s
done
Bytes transferred = 534240 (826e0 hex)
=> sf probe
SF: Detected S25FL164K with page size 256 Bytes, erase size 64 KiB, total 8 MiB
=> sf update 0x1000000 0 $filesize
device 0 offset 0x0, size 0x826e0
534240 bytes written, 0 bytes skipped in 10.563s, speed 51765 B/s

fix default variables and boot from mmc (I did 4 leds rescue before)

env default -a
saveenv
run mmcboot

rescue image

root@x230:/var/tftp# wget https://repo.turris.cz/hbs/omnia/packages/turrispackages/rescue-image_3.4-1_arm_cortex-a9_vfpv3-d16.ipk
root@x230:/var/tftp# mkdir tmp
root@x230:/var/tftp# cd tmp/
root@x230:/var/tftp/tmp# tar xvf ../rescue-image_3.4-1_arm_cortex-a9_vfpv3-d16.ipk
./debian-binary
./data.tar.gz
./control.tar.gz
root@x230:/var/tftp/tmp# tar xvf data.tar.gz
./
./usr/
./usr/share/
./usr/share/rescue-image/
./usr/share/rescue-image/image.fit
./usr/share/rescue-image/image.fit.lzma
root@x230:/var/tftp/tmp# cp usr/share/rescue-image/image.fit.lzma ../

now flash new rescue

=> tftpboot ${kernel_addr_r} image.fit.lzma
Using neta2 device
TFTP from server 192.168.4.1; our IP address is 192.168.4.113
Filename 'image.fit.lzma'.
Load address: 0x800000
Loading: #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         ###########################
         2.4 MiB/s
done
Bytes transferred = 6115919 (5d524f hex)

=> sf probe
SF: Detected S25FL164K with page size 256 Bytes, erase size 64 KiB, total 8 MiB
=> sf update ${kernel_addr_r} 0x00100000 ${filesize}
device 0 offset 0x5d524f, size 0x22adb1
SPI flash failed in erase step

update from shell

opkg install u-boot-omnia
opkg install rescue-image

root@turris:~# nor-update -d
Verifying /dev/mtd0 against /usr/share/omnia/uboot-devel ...
a107291f748c9b3d9d96dd718e3e471a - /dev/mtd0
15b3b8e4100351677e85b983ef659921 - /usr/share/omnia/uboot-devel
Failed
Unlocking /dev/mtd0 ...
Erasing /dev/mtd0 ...

Writing from /usr/share/omnia/uboot-devel to /dev/mtd0 ...
Verifying /dev/mtd1 against /usr/share/rescue-image/image.fit.lzma ...
1ea91207d0fbd4479bb4c8b4a3957371 - /dev/mtd1
82194bc8fc95193cc3f3491a047b0c88 - /usr/share/rescue-image/image.fit.lzma
Failed
Unlocking /dev/mtd1 ...
Erasing /dev/mtd1 ...

Writing from /usr/share/rescue-image/image.fit.lzma to /dev/mtd1 ...

This will make route unbootable :-(

Reflash router via usb https://docs.turris.cz/hw/omnia/rescue-modes/#re-flash-router

permalink
innbox v80

pictures

position of plastic clips to unclip after removing screws

innobox-v80-case-clips-20210522_192312.jpg

top of board

innobox-v80-top-20210522_192339.jpg

bottom of board

innobox-v80-back-20210522_192256.jpg

software version

Hardware version: 1.0
Active image: 2
Firmware image 1: 1.0.839
Firmware image 2: 1.1.966
Checksum of image 1: 34e4b3948d00a869d961283510a7eb08
Checksum of image 2: a6e08754c908c237d1539cb143611697
Firmware bootloader: 1.9
CRC of bootloader: a6e08754c908c237d1539cb143611697

serial

4 pins, pin 1 marked with triangle

1: TX
2: RX
3: GND
4: 3V3 (?)

serial output

(partial)

BGA IC
Xtal:1
DDR3 init.
DRAMC init done.
Calculate size.
DRAM size=128MB
Set new TRFC.

7512DRAMC V1.2.2 (0)


EN751221 at Fri Apr 16 11:48:25 CST 2021 version 1.9 free bootbase

Memory size 128MB

Set SPI Clock to 50 Mhz
spi_nand_probe: mfr_id=0xc8, dev_id=0x21
Using Flash ECC.
Detected SPI NAND Flash : _SPI_NAND_DEVICE_ID_F50L1G, Flash Size=0x8000000
bmt pool size: 81
BMT & BBT Init Success


>>>> [get_env_info] hw_id:InnboxV80_PW2
>>>> [set_gpio_define] g_hw_id:InnboxV80_PW2
Reset button GPIO is: 0
Press any key in 3 secs to enter boot command mode.
............................................................

Invalid Power GPIO, just return and don't turn on Power LED

NAND FLASH

>>>> CTC: boot_flag_addr: 53e0fff; flag: 1 version_addr:53e1000 version:1.9<FF><FF><FF><FF>

==> boot flag = 1
Decompress to 80002000 free_mem_ptr=80E00000 free_mem_ptr_end=807B0000
from slave
Uncompressing [LZMA] ...  done.
Initializing cgroup subsys cpuset
Initializing cgroup subsys cpu
Initializing cgroup subsys cpuacct
Linux version 3.18.21 (iskratel@2d7d74f016e9) (gcc version 4.6.3 (Buildroot 2015.08.1) ) #3 SMP Fri Apr 16 11:32:58 CST 2021
ISPRAM0: PA=00770000,Size=00010000,enabled
Config7: 0x80080500
memsize:120MB
EcoNet EN751221 SOC prom init
bootconsole [early0] enabled
CPU0 revision is: 00019558 (MIPS 34Kc)
Determined physical RAM map:
 memory: 077fe000 @ 00002000 (usable)
Wasting 64 bytes for tracking 2 unused pages
Zone ranges:
  Normal   [mem 0x00002000-0x077fffff]
Movable zone start for each node
Early memory node ranges
  node   0: [mem 0x00002000-0x077fffff]
Initmem setup node 0 [mem 0x00002000-0x077fffff]
Detected 1 available secondary CPU(s)
Primary instruction cache 64kB, VIPT, 4-way, linesize 32 bytes.
Primary data cache 32kB, 4-way, VIPT, cache aliases, linesize 32 bytes
PERCPU: Embedded 9 pages/cpu @810f3000 s5664 r8192 d23008 u36864
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 30478
Kernel command line:  es=1
PID hash table entries: 512 (order: -1, 2048 bytes)
Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
Writing ErrCtl register=0002e01a
Readback ErrCtl register=0002e01a
nmi base is 81124200
Memory: 110280K/122872K available (7640K kernel code, 1290K rwdata, 1624K rodata, 304K init, 551K bss, 12592K reserved)
SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
Hierarchical RCU implementation.
NR_IRQS:64

tc3162_time_init: Init bus timeout and watchdog
plat_set_irq_affinity: cpu 0
plat_set_irq_affinity: cpu 0 vpe_id 0
plat_set_irq_affinity: irq_vpe0 1 irq_vpe1 0, irq = 10
plat_set_irq_affinity: irq num 10
plat_set_irq_affinity: cpu 0
plat_set_irq_affinity: cpu 0 vpe_id 0
plat_set_irq_affinity: irq_vpe0 1 irq_vpe1 0, irq = 33
plat_set_irq_affinity: irq num 33
CPU frequency 900.00 MHz
plat_time_init: Entered, mips_timer_ack ptr is [80006dd4]
 Using 200.000 MHz high precision timer.
r4k_clockevent_init: setup_irq OK, irq is [31]
console [ttyS0] enabled
console [ttyS0] enabled
bootconsole [early0] disabled
bootconsole [early0] disabled
Calibrating delay loop... 597.60 BogoMIPS (lpj=2988032)
pid_max: default: 32768 minimum: 301

boot loader

bldr> ?

?                                   Print out help messages.
help                                Print out help messages.
go                                  Booting the linux kernel.
decomp                              Decompress kernel image to ram.
memrl <addr>                        Read a word from addr.
memwl <addr> <value>                Write a word to addr.
dump <addr> <len>                   Dump memory content.
jump <addr>                         Jump to addr.
flash <dst> <src> <len> <oob>       Write to flash from src to dst(oob: write nand oob if 1).
imginfo                             Show images info.
spinand_rwtest                      Flash Test
bdstore <flash dst> <bin src>       Do backdoor config store
bdshow                              Show backdoor config
bdswitch[1|0]                       Enable or disable backdoor function
ddrcalswitch[1|0]                   Enable or disable ddr calibration funciton
drambistswitch[0|1|2]               disable or enable, and quick or normal test
xmdm <addr> <len>                   Xmodem receive to addr.
miir <phyaddr> <reg>                Read ethernet phy reg.
miiw <phyaddr> <reg> <value>        Write ethernet phy reg.
cpufreq <freq num> / <m> <n>        Set CPU Freq <156~450>(freq has to be multiple of 6)
ipaddr <ip addr>                    Change modem's IP.
httpd                               Start Web Server
mtd
bldr> bdshow
back door config is not support NAND Flash
permalink
M8S PRO

Board sticker: M8S PRO R4 S912 3G 32G DDR4 DQ



M8S-PRO.jpg

It doesn't have button soldered, it works like power button in android

Serial port is marked on bottom of board (tx/rx are from cpu perspective)

probably: https://www.geekbuying.com/item/MECOOL-M8S-PRO-S912-KODI-17-0-4K-HDR10-3GB-DDR4-32GB-eMMC-TV-Box-380737.html

Android info

Android 7.1 bootlog from serial: m8s-android-bootlog.txt.gz

U-Boot 2015.01-g9331ff1-dirty (Mar 15 2018 - 16:16:24)

DRAM:  3 GiB
...
        aml_dt soc: gxm platform: q20xrmii variant: 3g
        dtb 0 soc: gxm   plat: q20xrmii   vari: 2g
        dtb 1 soc: gxm   plat: q20xrmii   vari: 3g
      Find match dtb: 1
...
parts: 10
00:      logo	0000000002000000 1
01:  recovery	0000000002000000 1
02:       rsv	0000000000800000 1
03:       tee	0000000000800000 1
04:     crypt	0000000002000000 1
05:      misc	0000000002000000 1
06:      boot	0000000002000000 1
07:    system	0000000080000000 1
08:     cache	0000000020000000 2
09:      data	ffffffffffffffff 4

M8SPRO:/ # uname -a
Linux localhost 3.14.29 #46 SMP PREEMPT Thu Apr 12 19:43:12 CST 2018 armv8l

M8SPRO:/ # cat /proc/cmdline
rootfstype=ramfs init=/init console=ttyS0,115200 no_console_suspend earlyprintk=aml-uart,0xc81004c0 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 androidboot.selinux=permissive logo=osd1,loaded,0x3d800000,1080p60hz maxcpus=8 vout=1080p60hz,enable hdmimode=1080p60hz cvbsmode=576cvbs hdmitx= cvbsdrv=0 pq= androidboot.firstboot=0 jtag=apao androidboot.hardware=amlogic mac=D0:76:58:0E:63:A3 androidboot.mac=D0:76:58:0E:63:A3 androidboot.slot_suffix=_a buildvariant=userdebug

M8SPRO:/ # cat /proc/cpuinfo
Processor	: AArch64 Processor rev 4 (aarch64)
processor	: 0
processor	: 1
processor	: 2
processor	: 3
processor	: 4
processor	: 5
processor	: 6
processor	: 7
Features	: fp asimd evtstrm aes pmull sha1 sha2 crc32 wp half thumb fastmult vfp edsp neon vfpv3 tlsi vfpv4 idiva idivt 
CPU implementer	: 0x41
CPU architecture: 8
CPU variant	: 0x0
CPU part	: 0xd03
CPU revision	: 4

Hardware	: Amlogic
Serial		: 220a82006da41365fedf301742726826

M8SPRO:/ # free
		total        used        free      shared     buffers
Mem:       2876604416  2210639872   665964544           0    31326208
-/+ buffers/cache:     2179313664   697290752
Swap:       524283904           0   524283904

M8SPRO:/ # df
ilesystem        1K-blocks    Used Available Use% Mounted on
mpfs               1404592     504   1404088   1% /dev
tmpfs               1404592       0   1404592   0% /mnt
/dev/block/system   2031440  973788   1057652  48% /system
/dev/block/data    26969964 3050864  23919100  12% /data
/dev/block/cache     507848    2860    504988   1% /cache
/dev/block/tee         5115      45      5070   1% /tee
/dev/fuse          26969964 3050864  23919100  12% /mnt/runtime/default/emulated
/dev/fuse          26969964 3050864  23919100  12% /mnt/runtime/read/emulated
/dev/fuse          26969964 3050864  23919100  12% /mnt/runtime/write/emulated


recovery sd

https://www.cnx-software.com/2016/11/19/how-to-create-a-bootable-recovery-sd-card-for-amlogic-tv-boxes/

amlogic info

http://www.linux-meson.com/doku.php

armbian

https://forum.armbian.com/topic/12162-single-armbian-image-for-rk-aml-aw-aarch64-armv8/

dpavlin@nuc:~/Downloads$ xzcat Armbian_20.09_Arm-64_bullseye_current_5.8.5.img.xz | dd iflag=fullblock oflag=direct conv=fsync status=progress bs=1M of=/dev/sdb
dpavlin@nuc:~/Downloads$ sudo mount /dev/sdb1 /mnt/sdb1/
dpavlin@nuc:~/Downloads$ cd /mnt/sdb1/

root@nuc:/mnt/sdb1# cp u-boot-s905x-s912 u-boot.ext

root@nuc:/mnt/sdb1# vi extlinux/extlinux.conf

root@nuc:/mnt/sdb1# grep -v '^#' extlinux/extlinux.conf
LABEL Armbian
LINUX /zImage
INITRD /uInitrd

FDT /dtb/amlogic/meson-gxm-q201.dtb
APPEND root=LABEL=ROOTFS rootflags=data=writeback rw console=ttyAML0,115200n8 console=tty0 no_console_suspend consoleblank=0 fsck.fix=yes fsck.repair=yes net.ifnames=0


Note that this board uses meson-gxm-q201.dtb which is internal rmii to make ethernet work!

issue reboot update from android shell to boot from sdcard

ath10k wifi sdio firmware

After booting, you will get error message about missing firmware:

[    7.861827] ath10k_sdio mmc2:0001:1: Failed to find firmware-N.bin (N between 2 and 6) from ath10k/QCA9377/hw1.0: -2
[    7.861838] ath10k_sdio mmc2:0001:1: could not fetch firmware files (-2)

Package firmware-atheros is installed, so it's a bit puzzeling what file is missing, however, if we go to

https://github.com/kvalo/ath10k-firmware.git

we can find sdio firmware at https://github.com/kvalo/ath10k-firmware/tree/master/QCA9377/hw1.0/untested

dpavlin@m8s:~/ath10k-firmware$ git remote -v
origin	https://github.com/kvalo/ath10k-firmware.git (fetch)
origin	https://github.com/kvalo/ath10k-firmware.git (push)

dpavlin@m8s:~/ath10k-firmware$ sudo cp QCA9377/hw1.0/untested/firmware-sdio-5.bin_WLAN.TF.1.1.1-00061-QCATFSWPZ-1 /lib/firmware/ath10k/QCA9377/hw1.0/firmware-sdio-5.bin

After running nmtui and configuring wifi it's available but dies after a while under load.

kernel source

https://github.com/150balbes/Amlogic_s905-kernel

u-boot source

https://github.com/150balbes/Amlogic_S905-u-boot

balbes150 updates

installing linux image and headers does return error, but works

https://users.armbian.com/balbes150/

gpiod

sudo apt install gpiod

button - gpio 2

root@arm-64:~# gpioget gpiochip0 2 # not pressed
1
root@arm-64:~# gpioget gpiochip0 2 # pressed
0

led - gpio 9

root@arm-64:~# gpioset gpiochip0 9=0 # red

root@arm-64:~# gpioset gpiochip0 9=1 # blue (default)

u-boot

old https://github.com/endlessm/u-boot-meson

I wanted serial console which seems to be missing from armbian build above

wiki seems to suggest repository

https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic

but we are going to use upstream u-boot

dpavlin@m8s:~/u-boot-amlogic$ git remote -v
github	https://github.com/u-boot/u-boot (fetch)

dpavlin@m8s:~/u-boot-amlogic$ libretech-cc_defconfig
dpavlin@m8s:~/u-boot-amlogic$ make -j 8
dpavlin@m8s:~/u-boot-amlogic$ cp u-boot.bin /boot/

abort u-boot with key press and boot new one with

fatload mmc 1 0x1000000 u-boot.bin
go 0x1000000

2020-10 status for amlogic

U-Boot: Porting and Maintaining a Bootloader for a Multimedia SoC Family - Neil Armstrong, BayLibre SAS

https://youtu.be/u0-swEMDFp0

permalink
ULX3S
Contents: [Dobrica Pavlinušić's random unstructured stuff]


first steps

Here I will try to document correct order to read documentation to get setup for ULX3S:

https://github.com/emard/ulx3s-bin/blob/master/README.md

There is also useful things from chat at ULX3S Lobby

udev rule

ujprog

git clone https://github.com/f32c/tools f32c-tools
cd f32c-tools/ujprog/
dpavlin@x200:/mnt/nuc/FPGA/f32c-tools/ujprog$ rm ujprog
dpavlin@x200:/mnt/nuc/FPGA/f32c-tools/ujprog$ make -f Makefile.linux
cc -Wall -D__linux__ -std=gnu99 -static ujprog.c /usr/lib/x86_64-linux-gnu/libftdi.a /usr/lib/x86_64-linux-gnu/libusb.a -o ujprog
dpavlin@x200:/mnt/nuc/FPGA/f32c-tools/ujprog$ sudo cp ujprog /usr/local/bin/

  • create udev rule

passthru to access esp32

source at https://github.com/emard/ulx3s-passthru

dpavlin@x200:/mnt/nuc/FPGA/ulx3s-bin/fpga/passthru/passthru-v20-85f$ ujprog -j flash ulx3s_85f_passthru.bit
ULX2S / ULX3S JTAG programmer v 3.0.92 (built Nov 19 2019 10:55:50)
Using USB cable: ULX3S FPGA 12K v3.0.3
[Wed Nov 20 18:02:01 2019] ftdi_sio ttyUSB0: FTDI USB Serial Device converter now disconnected from ttyUSB0
[Wed Nov 20 18:02:01 2019] ftdi_sio 1-5.2:1.0: device disconnected
Programming: 100%
Completed in 24.36 seconds.
[Wed Nov 20 18:02:25 2019] usb 1-5.2: reset full-speed USB device number 56 using ehci-pci
[Wed Nov 20 18:02:26 2019] ftdi_sio 1-5.2:1.0: FTDI USB Serial Device converter detected
[Wed Nov 20 18:02:26 2019] usb 1-5.2: Detected FT-X
[Wed Nov 20 18:02:26 2019] usb 1-5.2: FTDI USB Serial Device converter now attached to ttyUSB0


update size of your FPGA

dpavlin@x200:/mnt/nuc/FPGA/ulx3s-bin$ usb-jtag/linux-amd64/ftx_prog --product "ULX3S FPGA 85K v3.0.3"

power cycle board to get new usb id, test that it's supported by ujprog

dpavlin@x200:/mnt/nuc/FPGA/ulx3s-bin$ ujprog -r

esptool and esp32 booting problems

You should be using ecptool from ulx3s-bin repository to quite @emard from https://gitter.im/ulx3s/Lobby#dark-theme

OK then. If you have issues with ESP32 not booting with SD card but booting without SD card then then the fuse burn script from ulx3s-bin should be run. So far so good, you erased its flash, try linux. If no issue then can try to flash micropython and my new ESP32 OTA programmer ecp5.py end uftpd.py

I have wisely taken some esptool.py which works and frozen it in ulx3s, versions change all the time and maybe you took something in the middle of development action :)

install micropython

https://github.com/emard/esp32ecp5/

dpavlin@nuc:/nuc/FPGA$ git clone https://github.com/emard/esp32ecp5/
dpavlin@nuc:/nuc/FPGA$ cd esp32ecp5/
dpavlin@x200:/mnt/nuc/FPGA/esp32ecp5$ wget https://micropython.org/resources/firmware/esp32-idf3-20191120-v1.11-580-g973f68780.bin


It's important to erase flash or micropyhton will complain about corrupt fat filesystem like:

FAT filesystem appears to be corrupted. If you had important data there, you
may want to make a flash snapshot to try to recover it. Otherwise, perform
factory reprogramming of MicroPython firmware (completely erase flash, followed
by firmware programming).

dpavlin@x200:/mnt/nuc/FPGA/esp32ecp5$ ../ulx3s-bin/esp32/serial-uploader/esptool.py --chip esp32 --port /dev/ttyUSB0 erase_flash
esptool.py v2.6-beta1
Serial port /dev/ttyUSB0
Connecting....
Chip is ESP32D0WDQ6 (revision 1)
Features: WiFi, BT, Dual Core, 240MHz, VRef calibration in efuse, Coding Scheme None
MAC: a4:cf:12:55:c5:60
Uploading stub...
Running stub...
Stub running...
Erasing flash (this may take a while)...
Chip erase completed successfully in 8.7s
Hard resetting via RTS pin...


dpavlin@x200:/mnt/nuc/FPGA/esp32ecp5$ ../ulx3s-bin/esp32/serial-uploader/esptool.py --chip esp32 --port /dev/ttyUSB0 --baud 460800 write_flash -z 0x1000 esp32-idf3-20191120-v1.11-580-g973f68780.bin
esptool.py v2.6-beta1
Serial port /dev/ttyUSB0
Connecting....
Chip is ESP32D0WDQ6 (revision 1)
Features: WiFi, BT, Dual Core, 240MHz, VRef calibration in efuse, Coding Scheme None
MAC: a4:cf:12:55:c5:60
Uploading stub...
Running stub...
Stub running...
Changing baud rate to 460800
Changed.
Configuring flash size...
Auto-detected Flash size: 4MB
Compressed 1240192 bytes to 783187...
Wrote 1240192 bytes (783187 compressed) at 0x00001000 in 18.7 seconds (effective 529.3 kbit/s)...
Hash of data verified.

Leaving...
Hard resetting via RTS pin...

dpavlin@x200:/mnt/nuc/FPGA/esp32ecp5$ microcom -p /dev/ttyUSB0
connected to /dev/ttyUSB0
Escape character: Ctrl-\
Type the escape character to get to the prompt.

>>>
> help()
Welcome to MicroPython on the ESP32!

For generic online docs please visit http://docs.micropython.org/

For access to the hardware use the 'machine' module:

import machine
pin12 = machine.Pin(12, machine.Pin.OUT)
pin12.value(1)
pin13 = machine.Pin(13, machine.Pin.IN, machine.Pin.PULL_UP)
print(pin13.value())
i2c = machine.I2C(scl=machine.Pin(21), sda=machine.Pin(22))
i2c.scan()
i2c.writeto(addr, b'1234')
i2c.readfrom(addr, 4)

Basic WiFi configuration:

import network
sta_if = network.WLAN(network.STA_IF); sta_if.active(True)
sta_if.scan()                             # Scan for available access points
sta_if.connect("<AP_name>", "<password>") # Connect to an AP
sta_if.isconnected()                      # Check for successful connection

Control commands:
  CTRL-A        -- on a blank line, enter raw REPL mode
  CTRL-B        -- on a blank line, enter normal REPL mode
  CTRL-C        -- interrupt a running program
  CTRL-D        -- on a blank line, do a soft reset of the board
  CTRL-E        -- on a blank line, enter paste mode

For further help on a specific object, type help(obj)
For a list of available modules, type help('modules')

webrepl

dpavlin@klin:/klin/FPGA$ git clone https://github.com/hyperglitch/webrepl



You can send files from command-line:

dpavlin@x200:/mnt/nuc/FPGA/webrepl$ ./webrepl_cli.py -p ulx3s ../esp32ecp5/ecp5.py 192.168.3.130:/
op:put, host:192.168.3.130, port:8266, passwd:ulx3s.
../esp32ecp5/ecp5.py -> /ecp5.py
Remote WebREPL version: (1, 11, 0)
Sent 22777 of 22777 bytes
dpavlin@x200:/mnt/nuc/FPGA/webrepl$ ./webrepl_cli.py -p ulx3s ../esp32ecp5/uftpd.py 192.168.3.130:/
op:put, host:192.168.3.130, port:8266, passwd:ulx3s.
../esp32ecp5/uftpd.py -> /uftpd.py
Remote WebREPL version: (1, 11, 0)
Sent 19482 of 19482 bytes


open source toolchain

Just use kost's binary builds: https://github.com/alpin3/ulx3s/releases

Or nightly builds: https://github.com/open-tool-forge/fpga-toolchain/releases

this is old and needs update

dpavlin@klin:/klin/FPGA$ git clone https://github.com/SymbiFlow/prjtrellis
dpavlin@klin:/klin/FPGA/prjtrellis$ ./download-latest-db.sh 

dpavlin@klin:/klin/FPGA/prjtrellis$ cd libtrellis/
dpavlin@klin:/klin/FPGA/prjtrellis/libtrellis$ sudo apt-get install libpython3-dev libboost-python-dev libboost-filesystem-dev libboost-thread-dev libboost-program-options-dev
dpavlin@klin:/klin/FPGA/prjtrellis/libtrellis$ cmake -DCMAKE_INSTALL_PREFIX=/usr/local .
dpavlin@klin:/klin/FPGA/prjtrellis/libtrellis$ make
sudo make install


dpavlin@klin:/klin/FPGA/nextpnr$ cmake -DARCH=ecp5 -DBUILD_GUI=OFF -DTRELLIS_ROOT=../prjtrellis/ .
make
make install





diamond

https://github.com/jandob/lattice-diamond-archlinux/blob/master/eth0DummyToggle

docker

https://gitter.im/ulx3s/Lobby?at=5dff4b08d2dadb38935c570a

https://github.com/dok3r/diamond/

docker run -it -v /host/fpga:/fpga -- local /host/fpga will end up in /fpga in docker

yes path will be fine
you will be missing make
so inside container you need to yum install make
and yum install libxslt
export ETHMAC=b0:5a:da:XX:XX:XX
set your MAC
docker run -it -v /media/internal/FPGA:/fpga -e LM_LICENSE_FILE=/fpga/license.dat --mac-address=$ETHMAC --privileged --ipc host -v /dev/bus/usb/:/dev/bus/usb/ dok3r/diamond:latest
run docker
yum install make libxslt
go tu project inside fpga folder and find makefile for diamond and then just make

then you share it with docker container with -v /yourHOSTfpgadir:/fpgadockerdir -e LM_LICENSE_FILE=/fpgadockerdir
for version you need to use like this dok3r/diamond:version
versions are here
https://hub.docker.com/r/dok3r/diamond/tags
docker run -it -v /media/internal/FPGA:/fpga -e LM_LICENSE_FILE=/fpga/license.dat --mac-address=$ETHMAC --privileged --ipc host -v /dev/bus/usb/:/dev/bus/usb/ dok3r/diamond:v3.7
like this
Not understanding -v /media/internal/FPGA
that is my local FPGA folder with samples and license.dat
it will mount on docker /fpga
and I see now that I need to share prjtrallis folder to docker so it can do ecppll
docker run -it -v /media/internal/FPGA:/fpga -v /local/prjtrellis/libtrellis:/mt/scratch/tmp/openfpga/prjtrellis/libtrellis -e LM_LICENSE_FILE=/fpga/license.dat --mac-address=$ETHMAC --privileged --ipc host -v /dev/bus/usb/:/dev/bus/usb/ dok3r/diamond:v3.7
but for that we will need @kost
we probably need ecppll and tools already there and compiled with centos- maybe just binaries

NES

https://gitter.im/ulx3s/Lobby?at=5de033f49319bb5190a9c3b6

oberon

https://gitter.im/ulx3s/Lobby?at=5e007d1e8897197969e3331c

So, I have now managed to build oberon with diamond 3.7.
What I have to do is:

1. Build it with diamond 3.11, which fails
2. mv clocks clocks_save
3. make clean
4. cp -r clocks_save clocks
5. run docker for diamond 3.7
6. edit synpbase/bin/config/platform_check to allow 5.* linux.
7. make
8. Use ujprog in host linux to upload generated bit file

Thanks @kost for adding for adding make and libxslt to the docker image. It would be useful if you could patch the platform_check to allow versions before 3.11 to run on 5.* linux.
I got a lot of errors in the diamond 3.7 docker build, but the .bit file was created.
I can now run oberon and can see windows on the screen, but I don't have a working mouse or keyboard. I would need Goran's USB board to get both mouse and keyboard.
@lawrie i fixed in latest v3.7 - just make sure that you're running latest:

docker pull dok3r/diamond:v3.7

woohoo! Cool
@kost I pulled the latest v3.7 about 10 minutes ago, but still had to edit platform_check.
synpbase/bin/config/platform_check has:

        case $VERSION in
            4.* | 3.* | 2.4.* | 2.6.* )

It needs:

        case $VERSION in
            5.* | 4.* | 3.* | 2.4.* | 2.6.* )

I did the docker pull to make sure I had the latest version.
I changed oberon makefile to generate clocks in already existing directory to get rid of annoying mkdir clocks
In my instructions above it is safer to do make ECPPLL=echo in docker, so that it does not try to use ecppll, but uses the saved clocks that were generated on host linux.

21f repack from 25f image

ecpunpack --input ulx3s_25.bit --textcfg ulx3s_12f.config --idcode 0x41111043
ecppack --input ulx3s_12f.config --bit ulxs3_12f.bit --idcode 0x21111043


compress bitstream

ecppack --compress

esp32ps2

https://github.com/emard/esp32ps2

saxonsoc

linux

Instructions at https://github.com/lawrie/saxonsoc-ulx3s-bin/tree/master/linux
work for me on 85f :-)

https://gitter.im/ulx3s/Lobby?at=5de8ba2f08d0c961b7f3a25f

git clone https://github.com/SpinalHDL/buildroot.git -b saxon buildroot
git clone https://github.com/SpinalHDL/linux.git -b vexriscv --depth 1 linux
cd buildroot
cp board/spinal/saxon_default/linux_nonet.config board/spinal/saxon_default/linux.config
# Add extra options to board/spinal/saxon_default/linux.config
make spinal_saxon_default_defconfig
make linux-rebuild all -j$(nproc)
output/host/bin/riscv32-linux-objcopy -O binary output/images/vmlinux output/images/Image
# Make sure Image is at least 116KB less than 4MB

85f version

https://gitter.im/ulx3s/Lobby?at=5dea74995ac7f22fb57055ae

https://github.com/lawrie/saxonsoc-ulx3s-bin/blob/master/linux/README.md

https://github.com/lawrie/saxonsoc-ulx3s-bin/tree/master/linux/u-boot

https://github.com/SpinalHDL/SaxonSoc/tree/dev/bsp/Ulx3sLinuxUboot

leds

https://gitter.im/ulx3s/Lobby?at=5dec101f46397c721ca4c814

#!/bin/sh
cd /sys/class/gpio
echo 488 > export
echo out > gpio488/direction
for i in 1 0 1 0 1 0
do
  sleep  0.1
  echo   $i > gpio488/value
done


slirp

https://gitter.im/ulx3s/Lobby?at=5df1467d0616d6515e20d197

modifications

https://gitter.im/ulx3s/Lobby?at=5dfced993e3f133894ca9b4b

u-boot config for 85f with 64M SDRAM

Modify bootcmd to include:

load mmc 0:1 0x80000000 /boot/uImage
load mmc 0:1 0x81EF0000 /boot/dtb
fdt add 0x81EF0000
fdt memory 0x80000000 0x04000000
bootm 0x80000000 - 0x81EF0000

ppp networking

smp support

https://gitter.im/ulx3s/Lobby?at=5f4ea80bd4f0f55ebbf6ec33

https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.1/bsp/radiona/ulx3s/smp

Instructions there need a bit of modification to run on blue 85f board with 64Mb of ram:

# Sourcing the build script
source SaxonSoc/bsp/radiona/ulx3s/smp/source.sh

# Clone opensbi, u-boot, linux, buildroot, openocd
saxon_clone

# Build the FPGA bitstream
saxon_standalone_compile bootloader CFLAGS_ARGS="-DSDRAM_TIMING=AS4C32M16SB_7TCN_ps"
SDRAM_SIZE=64 saxon_netlist
FPGA_SIZE=85 saxon_bitstream

# Build the firmware
saxon_opensbi
saxon_uboot
saxon_buildroot

# Build the programming tools
saxon_standalone_compile sdramInit CFLAGS_ARGS="-DSDRAM_TIMING=AS4C32M16SB_7TCN_ps"
saxon_openocd

Copy generated bitstream

dpavlin@klin:/klin/FPGA/saxonsoc$ cp SaxonSoc/hardware/synthesis/radiona/ulx3s/smp/bin/toplevel.bit saxon.bit
dpavlin@klin:/klin/FPGA/saxonsoc$ gzip -9 saxon.bit

Transfer it using ftp

ftp> put saxon.bit.gz
local: saxon.bit.gz remote: saxon.bit.gz
200 OK
150 Opened data connection.
226 Done.
359484 bytes sent in 10.27 secs (34.1994 kB/s)
ftp> site saxon.bit.gz

u-boot will fail to boot if you have rootfs on second partition

SDRAM init
OpenSBI copy
U-Boot copy
OpenSBI boot

OpenSBI v0.6-8-gd7b62b8
   ____                    _____ ____ _____
  / __ \                  / ____|  _ \_   _|
 | |  | |_ __   ___ _ __ | (___ | |_) || |
 | |  | | '_ \ / _ \ '_ \ \___ \|  _ < | |
 | |__| | |_) |  __/ | | |____) | |_) || |_
  \____/| .__/ \___|_| |_|_____/|____/_____|
        | |
        |_|

Platform Name          : VexRiscv SMP simulation
Platform HART Features : RV32AIMS
Platform Max HARTs     : 4
Current Hart           : 0
Firmware Base          : 0x80f80000
Firmware Size          : 84 KB
Runtime SBI Version    : 0.2

MIDELEG : 0x00000222
MEDELEG : 0x0000b101


U-Boot 2020.07-08304-gd361dd3997 (Sep 05 2020 - 09:45:52 +0200)

DRAM:  32 MiB
MMC:   spi@10020000:mmc@1: 0
Loading Environment from FAT... Unable to use mmc 0:1... In:    serial@10010000
Out:   serial@10010000
Err:   serial@10010000
Net:   No ethernet found.
Hit any key to stop autoboot:  0
Wrong Image Format for bootm command
ERROR: can't get kernel image!
=>

https://github.com/dok3r/ulx3s-saxonsoc/wiki/SaxonSoc-on-ULX3s

setenv bootcmd "load mmc 0:1 0x80000000 /boot/uImage;load mmc 0:1 0x80FF0000 /boot/dtb;fdt add 0x80FF0000;fdt memory 0x80000000 0x04000000;bootm 0x80000000 - 0x80FF0000"
setenv bootargs "rootwait console=hvc0 root=/dev/mmcblk0p2 init=/sbin/init mmc_core.use_spi_crc=0"
saveenv

Lawrie Griffiths @lawrie Sep 01 21:59

The new SaxonSoc is now working on a 12F for me. Here are the instructions to build from source - https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.1/bsp/radiona/ulx3s/smp
The images and bitstream are here - https://github.com/lawrie/saxonsoc-ulx3s-bin/tree/master/Smp
There is no sdcard image at the moment, but all the files are there for you to build your own.

ov7670 pmod

https://github.com/goran-mahovlic/fpga-odysseus/tree/master/projects/OV7670-HDMI

pmod pin mapping:

https://github.com/goran-mahovlic/fpga-odysseus/blob/master/projects/OV7670-HDMI/ulx3s.lpf#L335

SCCB Pullup Resistors

from https://github.com/westonb/OV7670-Verilog

The SCCB interface for the camera requires pull up resistors. You need to solder 4.7K resistors from the SIOD and SIOC pins on the camera to the 3.3V supply. You can do this yourself or have the staff in the EDS help you.

ov7670_rgb_yuv_320x240_colorfilter

https://github.com/JdeRobot/FPGA-robotics/tree/master/Projects/ComputerVision

nmigen

https://github.com/lawrie/ulx3s-nmigen-examples/blob/master/image/camtest.py

csi

https://twitter.com/mad_archer_/status/1231249513509261313

https://github.com/libv/fosdem-video-linux

litex

(just links, need to test it)

spiram

https://gitter.im/ulx3s/Lobby?at=5ef22d4c54d7862dc4a42395

@Speccery thereis also commandline "spiram.py" for some low-level inspection, so to reset TI this works for me

spiram.poke(0x100008,bytearray(0xFC))
spiram.poke(0x100008,bytearray(0xFF))

and to read bytes

spiram.peek(0,16)

bytearray(b'\x83\xe0\x00$\x83\xc0\t\x00\x83\xc0\n\x920\xaa\x04`')

led

ftx_prog --cbus 3 DRIVE_0 # green OFF

ftx_prog --cbus 3 SLEEP # green ON if enumerated

This is active after power cycle

micropython blue led

>>> from machine import Pin
>>> led=Pin(5,Pin.OUT)
>>> led.on() # upali plavu
>>> led.off() # ugasi plavu

micropython

from upysh import *


TODO

try various projects for ulx3s

c64

part of https://github.com/lawrie/ulx3s_retro

https://github.com/emard/ulx3s_c64

dpavlin@klin:/klin/FPGA/ulx3s_c64/proj$ time make FPGA_SIZE=25




tfmicro on LiteX/VexRiscv

https://github.com/dlobato/tfmicro-on-litex-vexriscv

ML CNN accelerator

https://github.com/BracketMaster/maeri

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RD TC66C

RD TC66/TC66C Type-C PD trigger USB-C Voltmeter ammeter voltage 2 way current meter multimeter PD charger battery USB Tester

https://www.aliexpress.com/item/32968303350.html

https://sigrok.org/wiki/RDTech_TC66C

https://www.youtube.com/watch?v=rOlhibDUJgs

bluetooth le range is very losy, it's about 30cm so you almost have to put Android phone on top of TC66C to make it work :-(

TC66C Reverse Engineering

https://ralimtek.com/reverse%20engineering/software/tc66c-reverse-engineering/

https://github.com/Ralim/TC66C

newer version: https://github.com/Ircama/TC66C

pi@rpi2 ~/TC66C $ git remote -v
origin  https://github.com/Ircama/TC66C (fetch)
origin  https://github.com/Ircama/TC66C (push)
pi@rpi2 ~/TC66C $ git branch -a
* keyboard_mgmt
  master
  remotes/origin/HEAD -> origin/master
  remotes/origin/keyboard_mgmt
  remotes/origin/master

pi@rpi2 ~/TC66C $ sudo apt install python3-curtsies

pi@rpi2 ~/TC66C $ sudo pip3 install bluepy

pi@rpi2 ~/TC66C $ sudo ./scan.py


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TC358743XBG


Board name: H2C-RPI-B01

HDMI interface to CSI-2 interface
Chip: TC358743XBG
Support TK1 full-featured expansion board
Support Raspberry Pi (linux kernel version to 4.0 or above)
Limited by the performance of Raspberry itself, up to 1080p@25
Physical size: 65x30 mm, fixed hole position is the same as zero.

https://www.aliexpress.com/item/4000152180240.html

https://www.raspberrypi.org/forums/viewtopic.php?f=38&t=120702&start=400#p1339178

Lusya Upgraded version Raspberry Pi HDMI Adapter Board HDMI interface to CSI-2 TC358743XBG for 4B 3B 3B+ ZERO G11-011

/boot/config.txt

https://fluxcoil.net/hardwarerelated/raspberry_pi_4_tc358743

ensure that all options are enabled

   dtparam=i2c_arm=on
   dtparam=i2s=on
   dtparam=spi=on
   dtparam=i2c_vc=on
   dtparam=audio=on
   dtoverlay=vc4-fkms-v3d
   dtoverlay=dwc2
   dtoverlay=tc358743
   dtoverlay=tc358743-audio
   start_x=1
   gpu_mem=128 


setup

[    8.590920] tc358743 0-000f: tc358743 found @ 0x1e (bcm2835 I2C adapter)

root@pihdmi:/home/pi/CSI2_device_config# git remote -v
origin	https://github.com/6by9/CSI2_device_config (fetch)
origin	https://github.com/6by9/CSI2_device_config (push)

root@pihdmi:/home/pi/CSI2_device_config# cat edid.sh
v4l2-ctl --set-edid=file=1080P50EDID.txt --fix-edid-checksums

root@pihdmi:/home/pi/CSI2_device_config# sh -x edid.sh
+ v4l2-ctl --set-edid=file=1080P50EDID.txt --fix-edid-checksums

CTA-861 Header
  IT Formats Underscanned: yes
  Audio:                   yes
  YCbCr 4:4:4:             no
  YCbCr 4:2:2:             no

HDMI Vendor-Specific Data Block
  Physical Address:        3.0.0.0
  YCbCr 4:4:4 Deep Color:  no
  30-bit:                  no
  36-bit:                  no
  48-bit:                  no

CTA-861 Video Capability Descriptor
  RGB Quantization Range:  yes
  YCC Quantization Range:  no
  PT:                      Supports both over- and underscan
  IT:                      Supports both over- and underscan
  CE:                      Supports both over- and underscan


https://fluxcoil.net/hardwarerelated/raspberry_pi_4_tc358743

H5a650680b5f549749cce0a1a1f258bc2d.png

Hf9554fe5db464123bc629f548d89b606S.jpg

ustreamer

pi@pihdmi:~ $ git clone --depth=1 https://github.com/pikvm/ustreamer
pi@pihdmi:~ $ cd ustreamer/
pi@pihdmi:~/ustreamer $ make WITH_OMX=1
pi@pihdmi:~/ustreamer $ ./ustreamer --dv-timings --device=/dev/video0 --format=uyvy --encoder=omx \
 --workers=3 --persistent --drop-same-frames=30 --host=0.0.0.0 --port=8080
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Xiaomi Mijia Bluetooth Thermometer
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