Dobrica Pavlinušić's random unstructured stuff
ULX3S: Revision 4
first stepsHere I will try to document correct order to read documentation to get setup for ULX3S: https://github.com/emard/ulx3s-bin/blob/master/README.md udev ruleujproggit clone https://github.com/f32c/tools f32c-tools cd f32c-tools/ujprog/ dpavlin@x200:/mnt/nuc/FPGA/f32c-tools/ujprog$ rm ujprog dpavlin@x200:/mnt/nuc/FPGA/f32c-tools/ujprog$ make -f Makefile.linux cc -Wall -D__linux__ -std=gnu99 -static ujprog.c /usr/lib/x86_64-linux-gnu/libftdi.a /usr/lib/x86_64-linux-gnu/libusb.a -o ujprog dpavlin@x200:/mnt/nuc/FPGA/f32c-tools/ujprog$ sudo cp ujprog /usr/local/bin/
passthru to access esp32dpavlin@x200:/mnt/nuc/FPGA/ulx3s-bin/fpga/passthru/passthru-v20-85f$ ujprog -j flash ulx3s_85f_passthru.bit ULX2S / ULX3S JTAG programmer v 3.0.92 (built Nov 19 2019 10:55:50) Using USB cable: ULX3S FPGA 12K v3.0.3 [Wed Nov 20 18:02:01 2019] ftdi_sio ttyUSB0: FTDI USB Serial Device converter now disconnected from ttyUSB0 [Wed Nov 20 18:02:01 2019] ftdi_sio 1-5.2:1.0: device disconnected Programming: 100% Completed in 24.36 seconds. [Wed Nov 20 18:02:25 2019] usb 1-5.2: reset full-speed USB device number 56 using ehci-pci [Wed Nov 20 18:02:26 2019] ftdi_sio 1-5.2:1.0: FTDI USB Serial Device converter detected [Wed Nov 20 18:02:26 2019] usb 1-5.2: Detected FT-X [Wed Nov 20 18:02:26 2019] usb 1-5.2: FTDI USB Serial Device converter now attached to ttyUSB0 update size of your FPGAdpavlin@x200:/mnt/nuc/FPGA/ulx3s-bin$ usb-jtag/linux-amd64/ftx_prog --product "ULX3S FPGA 85K v3.0.3" power cycle board to get new usb id, test that it's supported by ujprog dpavlin@x200:/mnt/nuc/FPGA/ulx3s-bin$ ujprog -r install micropythonhttps://github.com/emard/esp32ecp5/ dpavlin@nuc:/nuc/FPGA$ git clone https://github.com/emard/esp32ecp5/ dpavlin@nuc:/nuc/FPGA$ cd esp32ecp5/ dpavlin@x200:/mnt/nuc/FPGA/esp32ecp5$ wget https://micropython.org/resources/firmware/esp32-idf3-20191120-v1.11-580-g973f68780.bin dpavlin@x200:/mnt/nuc/FPGA/esp32ecp5$ ../ulx3s-bin/esp32/serial-uploader/esptool.py --chip esp32 --port /dev/ttyUSB0 --baud 460800 write_flash -z 0x1000 esp32-idf3-20191120-v1.11-580-g973f68780.bin esptool.py v2.6-beta1 Serial port /dev/ttyUSB0 Connecting.... Chip is ESP32D0WDQ6 (revision 1) Features: WiFi, BT, Dual Core, 240MHz, VRef calibration in efuse, Coding Scheme None MAC: a4:cf:12:55:c5:60 Uploading stub... Running stub... Stub running... Changing baud rate to 460800 Changed. Configuring flash size... Auto-detected Flash size: 4MB Compressed 1240192 bytes to 783187... Wrote 1240192 bytes (783187 compressed) at 0x00001000 in 18.7 seconds (effective 529.3 kbit/s)... Hash of data verified. Leaving... Hard resetting via RTS pin... open source toolchaindpavlin@klin:/klin/FPGA$ git clone https://github.com/SymbiFlow/prjtrellis dpavlin@klin:/klin/FPGA/prjtrellis$ ./download-latest-db.sh dpavlin@klin:/klin/FPGA/prjtrellis$ cd libtrellis/ dpavlin@klin:/klin/FPGA/prjtrellis/libtrellis$ sudo apt-get install libpython3-dev libboost-python-dev libboost-filesystem-dev libboost-thread-dev libboost-program-options-dev dpavlin@klin:/klin/FPGA/prjtrellis/libtrellis$ cmake -DCMAKE_INSTALL_PREFIX=/usr/local . dpavlin@klin:/klin/FPGA/prjtrellis/libtrellis$ make |