video

• https://www.youtube.com/watch?v=_1yrxrl61o4
• https://www.youtube.com/watch?v=kRTs6B-kEOE

git

dpavlin@klin:/klin/FPGA/CFU-Playground$ git remote -v
origin  https://github.com/google/CFU-Playground.git (fetch)
origin  https://github.com/google/CFU-Playground.git (push)
dpavlin@klin:/klin/FPGA/CFU-Playground$ git submodule init
dpavlin@klin:/klin/FPGA/CFU-Playground$ git submodule update

ulx3s board

https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/radiona_ulx3s.py

dpavlin@klin:/klin/FPGA/CFU-Playground$ find . -name radiona_ulx3s.py
./third_party/python/litex_boards/litex_boards/targets/radiona_ulx3s.py
./third_party/python/litex_boards/litex_boards/platforms/radiona_ulx3s.py
# edit fpga settings here
dpavlin@klin:/klin/FPGA/CFU-Playground$ vi ./third_party/python/litex_boards/litex_boards/targets/radiona_ulx3s.py

build

klin:/klin/FPGA/CFU-Playground/proj/avg_pdti8# cat env.sh
#!/bin/sh -xe

echo https://github.com/google/CFU-Playground

export PATH=/klin/FPGA/saxonsoc/xpack-riscv-none-embed-gcc-8.3.0-1.2/bin/:/klin/FPGA/saxonsoc/riscv64-unknown-elf-gcc-20171231-x86_64-linux-centos6/bin/:$PATH
export TARGET=radiona_ulx3s
make prog

sumulation

dpavlin@klin:/klin/FPGA/CFU-Playground/proj/avg_pdti8$ time make PLATFORM=sim load -j 4