Dobrica Pavlinušić's random unstructured stuff
ULX3S: Revision 54
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^ first steps Here I will try to document correct order to read documentation to get setup for ULX3S: https://github.com/emard/ulx3s-bin/blob/master/README.md ^^ udev rule ^^ ujprog .pre git clone https://github.com/f32c/tools f32c-tools cd f32c-tools/ujprog/ dpavlin@x200:/mnt/nuc/FPGA/f32c-tools/ujprog$ rm ujprog dpavlin@x200:/mnt/nuc/FPGA/f32c-tools/ujprog$ make -f Makefile.linux cc -Wall -D__linux__ -std=gnu99 -static ujprog.c /usr/lib/x86_64-linux-gnu/libftdi.a /usr/lib/x86_64-linux-gnu/libusb.a -o ujprog dpavlin@x200:/mnt/nuc/FPGA/f32c-tools/ujprog$ sudo cp ujprog /usr/local/bin/ .pre * create udev rule ^^ passthru to access esp32 source at https://github.com/emard/ulx3s-passthru .pre dpavlin@x200:/mnt/nuc/FPGA/ulx3s-bin/fpga/passthru/passthru-v20-85f$ ujprog -j flash ulx3s_85f_passthru.bit ULX2S / ULX3S JTAG programmer v 3.0.92 (built Nov 19 2019 10:55:50) Using USB cable: ULX3S FPGA 12K v3.0.3 [Wed Nov 20 18:02:01 2019] ftdi_sio ttyUSB0: FTDI USB Serial Device converter now disconnected from ttyUSB0 [Wed Nov 20 18:02:01 2019] ftdi_sio 1-5.2:1.0: device disconnected Programming: 100% Completed in 24.36 seconds. [Wed Nov 20 18:02:25 2019] usb 1-5.2: reset full-speed USB device number 56 using ehci-pci [Wed Nov 20 18:02:26 2019] ftdi_sio 1-5.2:1.0: FTDI USB Serial Device converter detected [Wed Nov 20 18:02:26 2019] usb 1-5.2: Detected FT-X [Wed Nov 20 18:02:26 2019] usb 1-5.2: FTDI USB Serial Device converter now attached to ttyUSB0 .pre ^^ update size of your FPGA .pre dpavlin@x200:/mnt/nuc/FPGA/ulx3s-bin$ usb-jtag/linux-amd64/ftx_prog --product "ULX3S FPGA 85K v3.0.3" .pre power cycle board to get new usb id, test that it's supported by ujprog .pre dpavlin@x200:/mnt/nuc/FPGA/ulx3s-bin$ ujprog -r .pre ^^ esptool and esp32 booting problems You should be using ecptool from ulx3s-bin repository to quite @emard from https://gitter.im/ulx3s/Lobby#dark-theme > OK then. If you have issues with ESP32 not booting with SD card but booting without SD card then then the fuse burn script from ulx3s-bin should be run. So far so good, you erased its flash, try linux. If no issue then can try to flash micropython and my new ESP32 OTA programmer ecp5.py end uftpd.py > I have wisely taken some esptool.py which works and frozen it in ulx3s, versions change all the time and maybe you took something in the middle of development action :) ^^ install micropython https://github.com/emard/esp32ecp5/ .pre dpavlin@nuc:/nuc/FPGA$ git clone https://github.com/emard/esp32ecp5/ dpavlin@nuc:/nuc/FPGA$ cd esp32ecp5/ dpavlin@x200:/mnt/nuc/FPGA/esp32ecp5$ wget https://micropython.org/resources/firmware/esp32-idf3-20191120-v1.11-580-g973f68780.bin .pre It's important to erase flash or micropyhton will complain about corrupt fat filesystem like: FAT filesystem appears to be corrupted. If you had important data there, you may want to make a flash snapshot to try to recover it. Otherwise, perform factory reprogramming of MicroPython firmware (completely erase flash, followed by firmware programming). .pre dpavlin@x200:/mnt/nuc/FPGA/esp32ecp5$ ../ulx3s-bin/esp32/serial-uploader/esptool.py --chip esp32 --port /dev/ttyUSB0 erase_flash esptool.py v2.6-beta1 Serial port /dev/ttyUSB0 Connecting.... Chip is ESP32D0WDQ6 (revision 1) Features: WiFi, BT, Dual Core, 240MHz, VRef calibration in efuse, Coding Scheme None MAC: a4:cf:12:55:c5:60 Uploading stub... Running stub... Stub running... Erasing flash (this may take a while)... Chip erase completed successfully in 8.7s Hard resetting via RTS pin... dpavlin@x200:/mnt/nuc/FPGA/esp32ecp5$ ../ulx3s-bin/esp32/serial-uploader/esptool.py --chip esp32 --port /dev/ttyUSB0 --baud 460800 write_flash -z 0x1000 esp32-idf3-20191120-v1.11-580-g973f68780.bin esptool.py v2.6-beta1 Serial port /dev/ttyUSB0 Connecting.... Chip is ESP32D0WDQ6 (revision 1) Features: WiFi, BT, Dual Core, 240MHz, VRef calibration in efuse, Coding Scheme None MAC: a4:cf:12:55:c5:60 Uploading stub... Running stub... Stub running... Changing baud rate to 460800 Changed. Configuring flash size... Auto-detected Flash size: 4MB Compressed 1240192 bytes to 783187... Wrote 1240192 bytes (783187 compressed) at 0x00001000 in 18.7 seconds (effective 529.3 kbit/s)... Hash of data verified. Leaving... Hard resetting via RTS pin... dpavlin@x200:/mnt/nuc/FPGA/esp32ecp5$ microcom -p /dev/ttyUSB0 connected to /dev/ttyUSB0 Escape character: Ctrl-\ Type the escape character to get to the prompt. >>> > help() Welcome to MicroPython on the ESP32! For generic online docs please visit http://docs.micropython.org/ For access to the hardware use the 'machine' module: import machine pin12 = machine.Pin(12, machine.Pin.OUT) pin12.value(1) pin13 = machine.Pin(13, machine.Pin.IN, machine.Pin.PULL_UP) print(pin13.value()) i2c = machine.I2C(scl=machine.Pin(21), sda=machine.Pin(22)) i2c.scan() i2c.writeto(addr, b'1234') i2c.readfrom(addr, 4) Basic WiFi configuration: import network sta_if = network.WLAN(network.STA_IF); sta_if.active(True) sta_if.scan() # Scan for available access points sta_if.connect("<AP_name>", "<password>") # Connect to an AP sta_if.isconnected() # Check for successful connection Control commands: CTRL-A -- on a blank line, enter raw REPL mode CTRL-B -- on a blank line, enter normal REPL mode CTRL-C -- interrupt a running program CTRL-D -- on a blank line, do a soft reset of the board CTRL-E -- on a blank line, enter paste mode For further help on a specific object, type help(obj) For a list of available modules, type help('modules') .pre ^^ webrepl .pre dpavlin@klin:/klin/FPGA$ git clone https://github.com/hyperglitch/webrepl .pre You can send files from command-line: .pre dpavlin@x200:/mnt/nuc/FPGA/webrepl$ ./webrepl_cli.py -p ulx3s ../esp32ecp5/ecp5.py 192.168.3.130:/ op:put, host:192.168.3.130, port:8266, passwd:ulx3s. ../esp32ecp5/ecp5.py -> /ecp5.py Remote WebREPL version: (1, 11, 0) Sent 22777 of 22777 bytes dpavlin@x200:/mnt/nuc/FPGA/webrepl$ ./webrepl_cli.py -p ulx3s ../esp32ecp5/uftpd.py 192.168.3.130:/ op:put, host:192.168.3.130, port:8266, passwd:ulx3s. ../esp32ecp5/uftpd.py -> /uftpd.py Remote WebREPL version: (1, 11, 0) Sent 19482 of 19482 bytes .pre ^ open source toolchain Just use kost's binary builds: https://github.com/alpin3/ulx3s/releases *this is old and needs update* * https://github.com/SymbiFlow/prjtrellis .pre dpavlin@klin:/klin/FPGA$ git clone https://github.com/SymbiFlow/prjtrellis dpavlin@klin:/klin/FPGA/prjtrellis$ ./download-latest-db.sh dpavlin@klin:/klin/FPGA/prjtrellis$ cd libtrellis/ dpavlin@klin:/klin/FPGA/prjtrellis/libtrellis$ sudo apt-get install libpython3-dev libboost-python-dev libboost-filesystem-dev libboost-thread-dev libboost-program-options-dev dpavlin@klin:/klin/FPGA/prjtrellis/libtrellis$ cmake -DCMAKE_INSTALL_PREFIX=/usr/local . dpavlin@klin:/klin/FPGA/prjtrellis/libtrellis$ make sudo make install dpavlin@klin:/klin/FPGA/nextpnr$ cmake -DARCH=ecp5 -DBUILD_GUI=OFF -DTRELLIS_ROOT=../prjtrellis/ . make make install .pre ^ diamond https://github.com/jandob/lattice-diamond-archlinux/blob/master/eth0DummyToggle ^^ docker https://gitter.im/ulx3s/Lobby?at=5dff4b08d2dadb38935c570a https://github.com/dok3r/diamond/ .pre docker run -it -v /host/fpga:/fpga -- local /host/fpga will end up in /fpga in docker yes path will be fine you will be missing make so inside container you need to yum install make and yum install libxslt export ETHMAC=b0:5a:da:XX:XX:XX set your MAC docker run -it -v /media/internal/FPGA:/fpga -e LM_LICENSE_FILE=/fpga/license.dat --mac-address=$ETHMAC --privileged --ipc host -v /dev/bus/usb/:/dev/bus/usb/ dok3r/diamond:latest run docker yum install make libxslt go tu project inside fpga folder and find makefile for diamond and then just make then you share it with docker container with -v /yourHOSTfpgadir:/fpgadockerdir -e LM_LICENSE_FILE=/fpgadockerdir for version you need to use like this dok3r/diamond:version versions are here https://hub.docker.com/r/dok3r/diamond/tags docker run -it -v /media/internal/FPGA:/fpga -e LM_LICENSE_FILE=/fpga/license.dat --mac-address=$ETHMAC --privileged --ipc host -v /dev/bus/usb/:/dev/bus/usb/ dok3r/diamond:v3.7 like this Not understanding -v /media/internal/FPGA that is my local FPGA folder with samples and license.dat it will mount on docker /fpga and I see now that I need to share prjtrallis folder to docker so it can do ecppll docker run -it -v /media/internal/FPGA:/fpga -v /local/prjtrellis/libtrellis:/mt/scratch/tmp/openfpga/prjtrellis/libtrellis -e LM_LICENSE_FILE=/fpga/license.dat --mac-address=$ETHMAC --privileged --ipc host -v /dev/bus/usb/:/dev/bus/usb/ dok3r/diamond:v3.7 but for that we will need @kost we probably need ecppll and tools already there and compiled with centos- maybe just binaries .pre ^ NES https://gitter.im/ulx3s/Lobby?at=5de033f49319bb5190a9c3b6 * https://github.com/ironsteel/nes_ecp5 * flash arbitrary data to flash: https://github.com/ironsteel/tools/commit/cb0c43b6681a52f1cc19b6b70ddd587a307da90c#diff-3b94c2a26ac88b4b2363e058acf1852fR2281 * list of idcode: https://github.com/SymbiFlow/prjtrellis/blob/master/devices.json * ported to ulx3s: https://github.com/lawrie/nes_ecp5 ^ oberon https://gitter.im/ulx3s/Lobby?at=5e007d1e8897197969e3331c So, I have now managed to build oberon with diamond 3.7. What I have to do is: 1. Build it with diamond 3.11, which fails 2. mv clocks clocks_save 3. make clean 4. cp -r clocks_save clocks 5. run docker for diamond 3.7 6. edit synpbase/bin/config/platform_check to allow 5.* linux. 7. make 8. Use ujprog in host linux to upload generated bit file Thanks @kost for adding for adding make and libxslt to the docker image. It would be useful if you could patch the platform_check to allow versions before 3.11 to run on 5.* linux. I got a lot of errors in the diamond 3.7 docker build, but the .bit file was created. I can now run oberon and can see windows on the screen, but I don't have a working mouse or keyboard. I would need Goran's USB board to get both mouse and keyboard. @lawrie i fixed in latest v3.7 - just make sure that you're running latest: docker pull dok3r/diamond:v3.7 woohoo! Cool @kost I pulled the latest v3.7 about 10 minutes ago, but still had to edit platform_check. synpbase/bin/config/platform_check has: case $VERSION in 4.* | 3.* | 2.4.* | 2.6.* ) It needs: case $VERSION in 5.* | 4.* | 3.* | 2.4.* | 2.6.* ) I did the docker pull to make sure I had the latest version. I changed oberon makefile to generate clocks in already existing directory to get rid of annoying mkdir clocks In my instructions above it is safer to do make ECPPLL=echo in docker, so that it does not try to use ecppll, but uses the saved clocks that were generated on host linux. ^ 21f repack from 25f image .pre ecpunpack --input ulx3s_25.bit --textcfg ulx3s_12f.config --idcode 0x41111043 ecppack --input ulx3s_12f.config --bit ulxs3_12f.bit --idcode 0x21111043 .pre ^ compress bitstream .pre ecppack --compress .pre ^ esp32ps2 https://github.com/emard/esp32ps2 ^ saxonsoc ^^ linux Instructions at https://github.com/lawrie/saxonsoc-ulx3s-bin/tree/master/linux work for me on 85f :-) https://gitter.im/ulx3s/Lobby?at=5de8ba2f08d0c961b7f3a25f .pre git clone https://github.com/SpinalHDL/buildroot.git -b saxon buildroot git clone https://github.com/SpinalHDL/linux.git -b vexriscv --depth 1 linux cd buildroot cp board/spinal/saxon_default/linux_nonet.config board/spinal/saxon_default/linux.config # Add extra options to board/spinal/saxon_default/linux.config make spinal_saxon_default_defconfig make linux-rebuild all -j$(nproc) output/host/bin/riscv32-linux-objcopy -O binary output/images/vmlinux output/images/Image # Make sure Image is at least 116KB less than 4MB .pre ^^ 85f version https://gitter.im/ulx3s/Lobby?at=5dea74995ac7f22fb57055ae https://github.com/lawrie/saxonsoc-ulx3s-bin/blob/master/linux/README.md https://github.com/lawrie/saxonsoc-ulx3s-bin/tree/master/linux/u-boot https://github.com/SpinalHDL/SaxonSoc/tree/dev/bsp/Ulx3sLinuxUboot ^^ leds https://gitter.im/ulx3s/Lobby?at=5dec101f46397c721ca4c814 .pre #!/bin/sh cd /sys/class/gpio echo 488 > export echo out > gpio488/direction for i in 1 0 1 0 1 0 do sleep 0.1 echo $i > gpio488/value done .pre ^^ slirp https://gitter.im/ulx3s/Lobby?at=5df1467d0616d6515e20d197 ^^ modifications https://gitter.im/ulx3s/Lobby?at=5dfced993e3f133894ca9b4b ^^ i2c https://gitter.im/ulx3s/Lobby?at=5dfcf29acf771f7708ff69e9 It should not be that hard. I have i2c in SaxonSoc in other projects such as https://github.com/SpinalHDL/SaxonSoc/blob/dev/hardware/scala/saxon/board/blackice/BlackiceSocArduino.scala#L25 The generated board support packages include a generated dts, but it is not used yet and the simple i2c generator that I wrote does not generate the dts. There is a problem building SaxonSoc Linux, that some build randomly do not work. It seems to be something to do with SDRAM access. @Dolu1990 is about to redo the SDRAM access for the Ulx3s, which should make it more reliable and faster, as he plans to support double frequency access. There is a lot of information on the development of the u-boot version here , which might be useful to you - SpinalHDL/SaxonSoc#7 https://github.com/SpinalHDL/SaxonSoc/pull/7 I2c Linux support will also need a spinal.lib driver here - https://github.com/SpinalHDL/linux/tree/linux-5.0.y/drivers/i2c The terasic De1Soc version of SaxonSoc Linux has a dts entry for an led for disk access - https://github.com/SpinalHDL/buildroot/blob/saxon/board/spinal/saxon_default/spinal_saxon_default_de1_soc.dts#L194 We really need a better GPIO mapping for the Ulx3s. That might involve including adding a second gpio peripheral to the hardware (gpioB) and doing a better lpf file mapping to pins. It might mean increasing the niumbers of pins that support interrupts. It would be good to include access to the buttons and switches and to make it easy to add Pmods that need interrupt support like the enc28j60 one. ^^ u-boot config for 85f with 64M SDRAM Modify bootcmd to include: .pre load mmc 0:1 0x80000000 /boot/uImage load mmc 0:1 0x81EF0000 /boot/dtb fdt add 0x81EF0000 fdt memory 0x80000000 0x04000000 bootm 0x80000000 - 0x81EF0000 .pre ^^ ppp networking * https://github.com/dok3r/ulx3s-saxonsoc/wiki/ulx3s-networking * https://github.com/emard/esp32ppp ^ ov7670 pmod https://github.com/goran-mahovlic/fpga-odysseus/tree/master/projects/OV7670-HDMI pmod pin mapping: https://github.com/goran-mahovlic/fpga-odysseus/blob/master/projects/OV7670-HDMI/ulx3s.lpf#L335 ^^ SCCB Pullup Resistors from https://github.com/westonb/OV7670-Verilog The SCCB interface for the camera requires pull up resistors. You need to solder 4.7K resistors from the SIOD and SIOC pins on the camera to the 3.3V supply. You can do this yourself or have the staff in the EDS help you. ^ csi https://twitter.com/mad_archer_/status/1231249513509261313 https://github.com/libv/fosdem-video-linux ^ litex (just links, need to test it) * https://gojimmypi.blogspot.com/2020/03/litex-soft-cpu-on-ulx3s-reloading.html * https://github.com/timvideos/litex-buildenv/wiki/LiteX-for-Hardware-Engineers * https://github.com/enjoy-digital/litex ^ spiram https://gitter.im/ulx3s/Lobby?at=5ef22d4c54d7862dc4a42395 @Speccery thereis also commandline "spiram.py" for some low-level inspection, so to reset TI this works for me >>> spiram.poke(0x100008,bytearray([0xFC])) >>> spiram.poke(0x100008,bytearray([0xFF])) and to read bytes >>> spiram.peek(0,16) bytearray(b'\x83\xe0\x00$\x83\xc0\t\x00\x83\xc0\n\x920\xaa\x04`') ^ led .pre ftx_prog --cbus 3 DRIVE_0 # green OFF ftx_prog --cbus 3 SLEEP # green ON if enumerated .pre This is active after power cycle ^^ micropython blue led .pre >>> from machine import Pin >>> led=Pin(5,Pin.OUT) >>> led.on() # upali plavu >>> led.off() # ugasi plavu .pre ^ micropython .pre from upysh import * .pre ^ ecp5pll > Mario Hoffmann @hoffma_gitlab Aug 05 16:11 Hello, I wanted to have a 90 degree shifted clock. I was trying out the ecp5pll from @emard. I get it running and the clock adjustment seems to work, but somehow it does not get shifted for me. Is this currently not working with yosys and so forth, is there anything I have to take care of, or might it just be a bug on my side? Tried to search this chat a bit and just searched a bit on the internet but the things I found about it were quite old and not necessarily about my problem. Any ideas? I am using the vhdl version btw > emard @emard Aug 05 16:59 There's some order of signals and small delays between them for dynamic shifting to work. https://github.com/emard/ulx3s-misc/blob/master/examples/sdram/memtest_mister/hdl/top/top_memtest.v#L73 here is module to control phase shifts by pressing of BTN for testing of SDRAM with variable phase shift of the clock to chip > Mario Hoffmann @hoffma_gitlab Aug 05 17:01 alright, ill look at that. thanks > Mario Hoffmann @hoffma_gitlab Aug 05 17:53 Oh nice it works. My thinking was just a bit wrong and there was a little bug too. Thanks > emard @emard Aug 05 18:07 ecp5pll has possibility for fine-precision phase adjustment but this simple BTN module doesn't generate proper phaseloadreg signal https://github.com/emard/ulx3s-misc/blob/master/examples/sdram/memtest_mister/hdl/btn_ecp5pll_phase.v#L51 ^ display https://gitter.im/ulx3s/Lobby?at=5f3b7df7ee58011680b36cb0 > emard @emard Aug 18 09:06 SSD1331 96x64 is full featured OLED beautiful contrast, but currently best buy is ST7789 1.3" 240x240 LCD less contrast but more pix and less $. Do not solder directly the display. Solder female 7-pin header and plug the display. Mechanical stabilization can be 3D printed https://github.com/emard/ulx3s/tree/master/box it will "work" properly only if whole box is printed. There is no problem with heat normally to FPGA but SSD1331 with wrong software commands can become hot to fry fingers and smoke, it happened to me once, colors faded and I just replaced display. Onboard USB-SERIAL can provide 2nd JTAG channel for openocd debugger of RISCV processor it will work but it will be VERY slow (for debug single step ok, but for transferring Mbps no). ^ rtc https://gitter.im/ulx3s/Lobby?at=5f3b86a1a8c178017657caf6 > emard @emard Aug 18 09:43 Yes for RTC I first saw it "works" but after few reboots I found out that it resets to compile time or something. Core could consult onboard RTC using i2c and then set unix time integer counter which will continue ticking afterwards. For setting RTC we have esp32 and other options. Btw import ntptime; ntptime.settime() will set ESP32 localtime() from a pool of network NTP servers and then esp32 can initialize onboard RTC here I have played with this https://github.com/emard/ulx3s-misc/tree/master/examples/rtc/micropython-mcp7940n/esp32 ^ TODO try various projects for ulx3s * https://gitlab.com/pnru/cortex |