Board version: v7.0
SN74CBT3245APW 8bit bidirectional FET switches
UART RX is on J19, labelled key+ on the silk screen on the back
UART TX is on J1, pin 1.
LOCATE COMP "clock" SITE "P6";
LOCATE COMP "io_tx" SITE "F3";
LOCATE COMP "io_rx" SITE "M13";
basic example of litex on colorLight 5A-75B based on fpga_101/lab004
I don't want to load a new image onto this totally blind, so I used the prjtrellis tools (https://github.com/YosysHQ/prjtrellis/) to write a script (https://github.com/adamgreig/cl/blob/master/pins.py) which works out input/output/bidi for all pins used in any ECP5 bitstream. It found only one unused pin...